xe_mmio_read32(mmio, GFX_MSTR_IRQ);
}
-static void gt_irq_postinstall(struct xe_tile *tile)
+void xe_gt_irq_postinstall(struct xe_tile *tile)
{
struct xe_device *xe = tile_to_xe(tile);
struct xe_gt *mmio = tile->primary_gt;
xe_mmio_write32(mmio, GUC_SG_INTR_MASK, ~0);
}
-static void xelp_irq_postinstall(struct xe_device *xe, struct xe_tile *tile)
-{
- /* TODO: PCH */
-
- gt_irq_postinstall(tile);
-
- xelp_intr_enable(xe, true);
-}
-
static u32
gt_engine_identity(struct xe_device *xe,
struct xe_gt *mmio,
xe_mmio_read32(mmio, DG1_MSTR_TILE_INTR);
}
-static void dg1_irq_postinstall(struct xe_device *xe, struct xe_tile *tile)
-{
- gt_irq_postinstall(tile);
-
- if (tile->id == 0)
- dg1_intr_enable(xe, true);
-}
-
/*
* Top-level interrupt handler for Xe_LP+ and beyond. These platforms have
* a "master tile" interrupt register which must be consulted before the
mask_and_disable(tile, GU_MISC_IRQ_OFFSET);
}
-void xe_gt_irq_postinstall(struct xe_tile *tile)
-{
- struct xe_device *xe = tile_to_xe(tile);
-
- if (GRAPHICS_VERx100(xe) >= 1210)
- dg1_irq_postinstall(xe, tile);
- else
- xelp_irq_postinstall(xe, tile);
-}
-
static void xe_irq_postinstall(struct xe_device *xe)
{
struct xe_tile *tile;
*/
unmask_and_enable(xe_device_get_root_tile(xe),
GU_MISC_IRQ_OFFSET, GU_MISC_GSE);
+
+ /* Enable top-level interrupts */
+ if (GRAPHICS_VERx100(xe) >= 1210)
+ dg1_intr_enable(xe, true);
+ else
+ xelp_intr_enable(xe, true);
}
static irq_handler_t xe_irq_handler(struct xe_device *xe)
return err;
}
+ xe_irq_postinstall(xe);
+
err = drmm_add_action_or_reset(&xe->drm, irq_uninstall, xe);
if (err)
return err;