clocksource/drivers/timer-atmel-tcb: Rework 32khz clock selection

On all the supported SoCs, the slow clock is always ATMEL_TC_TIMER_CLOCK5,
avoid looking it up and pass it directly to setup_clkevents.

Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Link: https://lore.kernel.org/r/20200710230813.1005150-6-alexandre.belloni@bootlin.com

diff --git a/drivers/clocksource/timer-atmel-tcb.c b/drivers/clocksource/timer-atmel-tcb.c
index 7427b07..b255a4a 100644 (file)
--- a/drivers/clocksource/timer-atmel-tcb.c
+++ b/drivers/clocksource/timer-atmel-tcb.c
@@ -346,7 +346,7 @@ static void __init tcb_setup_single_chan(struct atmel_tc *tc, int mck_divisor_id
        writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
 }
 
-static const u8 atmel_tcb_divisors[5] = { 2, 8, 32, 128, 0, };
+static const u8 atmel_tcb_divisors[] = { 2, 8, 32, 128 };
 
 static const struct of_device_id atmel_tcb_of_match[] = {
        { .compatible = "atmel,at91rm9200-tcb", .data = (void *)16, },
@@ -362,7 +362,6 @@ static int __init tcb_clksrc_init(struct device_node *node)
        u64 (*tc_sched_clock)(void);
        u32 rate, divided_rate = 0;
        int best_divisor_idx = -1;
-       int clk32k_divisor_idx = -1;
        int bits;
        int i;
        int ret;
@@ -416,12 +415,6 @@ static int __init tcb_clksrc_init(struct device_node *node)
                unsigned divisor = atmel_tcb_divisors[i];
                unsigned tmp;
 
-               /* remember 32 KiHz clock for later */
-               if (!divisor) {
-                       clk32k_divisor_idx = i;
-                       continue;
-               }
-
                tmp = rate / divisor;
                pr_debug("TC: %u / %-3u [%d] --> %u\n", rate, divisor, i, tmp);
                if (best_divisor_idx > 0) {
@@ -467,7 +460,7 @@ static int __init tcb_clksrc_init(struct device_node *node)
                goto err_disable_t1;
 
        /* channel 2:  periodic and oneshot timer support */
-       ret = setup_clkevents(&tc, clk32k_divisor_idx);
+       ret = setup_clkevents(&tc, ATMEL_TC_TIMER_CLOCK5);
        if (ret)
                goto err_unregister_clksrc;