perf/cxlpmu: Add missing CXL 4.0 events

Add support for CXL 4.0 events that are exposed by the CPMU hardware
but not present in the driver. Such events are defined in Table 13-5
of the spec.

Signed-off-by: Harshal Thakkar <harshal.t@samsung.com>
[davidlohr: add missing throttle and queue occupancy events]
Signed-off-by: Davidlohr Bueso <dave@stgolabs.net>
Reviewed-by: Richard Cheng <icheng@nvidia.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Signed-off-by: Will Deacon <will@kernel.org>

diff --git a/drivers/perf/cxl_pmu.c b/drivers/perf/cxl_pmu.c
index 39b4655..1fc8385 100644 (file)
--- a/drivers/perf/cxl_pmu.c
+++ b/drivers/perf/cxl_pmu.c
@@ -77,6 +77,10 @@
 #define CXL_PMU_GID_S2M_NDR            0x0024
 #define CXL_PMU_GID_S2M_DRS            0x0025
 #define CXL_PMU_GID_DDR                        0x8000
+#define CXL_PMU_GID_QUEUE_OCC           0x8001
+#define CXL_PMU_GID_QUEUE_RESID         0x8002
+#define CXL_PMU_GID_RETRY_EVENTS        0x8003
+#define CXL_PMU_GID_THROTTLE            0x8004
 
 static int cxl_pmu_cpuhp_state_num;
 
@@ -385,13 +389,23 @@ static struct attribute *cxl_pmu_event_attrs[] = {
        CXL_PMU_EVENT_CXL_ATTR(m2s_req_memwrfwd,                CXL_PMU_GID_M2S_REQ, BIT(4)),
        CXL_PMU_EVENT_CXL_ATTR(m2s_req_memrdtee,                CXL_PMU_GID_M2S_REQ, BIT(5)),
        CXL_PMU_EVENT_CXL_ATTR(m2s_req_memrddatatee,            CXL_PMU_GID_M2S_REQ, BIT(6)),
+       CXL_PMU_EVENT_CXL_ATTR(m2s_req_meminvtee,               CXL_PMU_GID_M2S_REQ, BIT(7)),
        CXL_PMU_EVENT_CXL_ATTR(m2s_req_memspecrd,               CXL_PMU_GID_M2S_REQ, BIT(8)),
        CXL_PMU_EVENT_CXL_ATTR(m2s_req_meminvnt,                CXL_PMU_GID_M2S_REQ, BIT(9)),
        CXL_PMU_EVENT_CXL_ATTR(m2s_req_memcleanevict,           CXL_PMU_GID_M2S_REQ, BIT(10)),
+       CXL_PMU_EVENT_CXL_ATTR(m2s_req_meminvptee,              CXL_PMU_GID_M2S_REQ, BIT(11)),
+       CXL_PMU_EVENT_CXL_ATTR(m2s_req_memspecrdtee,            CXL_PMU_GID_M2S_REQ, BIT(12)),
+       CXL_PMU_EVENT_CXL_ATTR(m2s_req_teupdate,                CXL_PMU_GID_M2S_REQ, BIT(13)),
+       CXL_PMU_EVENT_CXL_ATTR(m2s_req_memclnevcttee,           CXL_PMU_GID_M2S_REQ, BIT(14)),
+       CXL_PMU_EVENT_CXL_ATTR(m2s_req_memclnevctu,             CXL_PMU_GID_M2S_REQ, BIT(15)),
        /* CXL rev 3.0 Table 3-35 M2S RwD Memory Opcodes */
        CXL_PMU_EVENT_CXL_ATTR(m2s_rwd_memwr,                   CXL_PMU_GID_M2S_RWD, BIT(1)),
        CXL_PMU_EVENT_CXL_ATTR(m2s_rwd_memwrptl,                CXL_PMU_GID_M2S_RWD, BIT(2)),
        CXL_PMU_EVENT_CXL_ATTR(m2s_rwd_biconflict,              CXL_PMU_GID_M2S_RWD, BIT(4)),
+       CXL_PMU_EVENT_CXL_ATTR(m2s_rwd_memrdfill,               CXL_PMU_GID_M2S_RWD, BIT(5)),
+       CXL_PMU_EVENT_CXL_ATTR(m2s_rwd_memwrtee,                CXL_PMU_GID_M2S_RWD, BIT(9)),
+       CXL_PMU_EVENT_CXL_ATTR(m2s_rwd_memwrptltee,             CXL_PMU_GID_M2S_RWD, BIT(10)),
+       CXL_PMU_EVENT_CXL_ATTR(m2s_rwd_memrdfilltee,            CXL_PMU_GID_M2S_RWD, BIT(13)),
        /* CXL rev 3.0 Table 3-38 M2S BIRsp Memory Opcodes */
        CXL_PMU_EVENT_CXL_ATTR(m2s_birsp_i,                     CXL_PMU_GID_M2S_BIRSP, BIT(0)),
        CXL_PMU_EVENT_CXL_ATTR(m2s_birsp_s,                     CXL_PMU_GID_M2S_BIRSP, BIT(1)),
@@ -406,15 +420,25 @@ static struct attribute *cxl_pmu_event_attrs[] = {
        CXL_PMU_EVENT_CXL_ATTR(s2m_bisnp_curblk,                CXL_PMU_GID_S2M_BISNP, BIT(4)),
        CXL_PMU_EVENT_CXL_ATTR(s2m_bisnp_datblk,                CXL_PMU_GID_S2M_BISNP, BIT(5)),
        CXL_PMU_EVENT_CXL_ATTR(s2m_bisnp_invblk,                CXL_PMU_GID_S2M_BISNP, BIT(6)),
+       CXL_PMU_EVENT_CXL_ATTR(s2m_bisnp_curtee,                CXL_PMU_GID_S2M_BISNP, BIT(8)),
+       CXL_PMU_EVENT_CXL_ATTR(s2m_bisnp_datatee,               CXL_PMU_GID_S2M_BISNP, BIT(9)),
+       CXL_PMU_EVENT_CXL_ATTR(s2m_bisnp_invtee,                CXL_PMU_GID_S2M_BISNP, BIT(10)),
+       CXL_PMU_EVENT_CXL_ATTR(s2m_bisnp_curblktee,             CXL_PMU_GID_S2M_BISNP, BIT(12)),
+       CXL_PMU_EVENT_CXL_ATTR(s2m_bisnp_datablktee,            CXL_PMU_GID_S2M_BISNP, BIT(13)),
+       CXL_PMU_EVENT_CXL_ATTR(s2m_bisnp_invblktee,             CXL_PMU_GID_S2M_BISNP, BIT(14)),
        /* CXL rev 3.1 Table 3-50 S2M NDR Opcodes */
        CXL_PMU_EVENT_CXL_ATTR(s2m_ndr_cmp,                     CXL_PMU_GID_S2M_NDR, BIT(0)),
        CXL_PMU_EVENT_CXL_ATTR(s2m_ndr_cmps,                    CXL_PMU_GID_S2M_NDR, BIT(1)),
        CXL_PMU_EVENT_CXL_ATTR(s2m_ndr_cmpe,                    CXL_PMU_GID_S2M_NDR, BIT(2)),
        CXL_PMU_EVENT_CXL_ATTR(s2m_ndr_cmpm,                    CXL_PMU_GID_S2M_NDR, BIT(3)),
        CXL_PMU_EVENT_CXL_ATTR(s2m_ndr_biconflictack,           CXL_PMU_GID_S2M_NDR, BIT(4)),
+       CXL_PMU_EVENT_CXL_ATTR(s2m_ndr_cmptee,                  CXL_PMU_GID_S2M_NDR, BIT(5)),
+       CXL_PMU_EVENT_CXL_ATTR(s2m_ndr_cmptee_s,                CXL_PMU_GID_S2M_NDR, BIT(6)),
+       CXL_PMU_EVENT_CXL_ATTR(s2m_ndr_cmptee_e,                CXL_PMU_GID_S2M_NDR, BIT(7)),
        /* CXL rev 3.0 Table 3-46 S2M DRS opcodes */
        CXL_PMU_EVENT_CXL_ATTR(s2m_drs_memdata,                 CXL_PMU_GID_S2M_DRS, BIT(0)),
        CXL_PMU_EVENT_CXL_ATTR(s2m_drs_memdatanxm,              CXL_PMU_GID_S2M_DRS, BIT(1)),
+       CXL_PMU_EVENT_CXL_ATTR(s2m_drs_memdatatee,              CXL_PMU_GID_S2M_DRS, BIT(2)),
        /* CXL rev 3.0 Table 13-5 directly lists these */
        CXL_PMU_EVENT_CXL_ATTR(ddr_act,                         CXL_PMU_GID_DDR, BIT(0)),
        CXL_PMU_EVENT_CXL_ATTR(ddr_pre,                         CXL_PMU_GID_DDR, BIT(1)),
@@ -423,6 +447,32 @@ static struct attribute *cxl_pmu_event_attrs[] = {
        CXL_PMU_EVENT_CXL_ATTR(ddr_refresh,                     CXL_PMU_GID_DDR, BIT(4)),
        CXL_PMU_EVENT_CXL_ATTR(ddr_selfrefreshent,              CXL_PMU_GID_DDR, BIT(5)),
        CXL_PMU_EVENT_CXL_ATTR(ddr_rfm,                         CXL_PMU_GID_DDR, BIT(6)),
+       /* CXL 4.0 Table 13-5 DDR add-on events opcodes */
+       CXL_PMU_EVENT_CXL_ATTR(ddr_cas_rd_ap,                   CXL_PMU_GID_DDR, BIT(7)),
+       CXL_PMU_EVENT_CXL_ATTR(ddr_cas_wr_ap,                   CXL_PMU_GID_DDR, BIT(8)),
+       CXL_PMU_EVENT_CXL_ATTR(ddr_refresh_all_banks,           CXL_PMU_GID_DDR, BIT(9)),
+       CXL_PMU_EVENT_CXL_ATTR(ddr_refresh_same_bank,           CXL_PMU_GID_DDR, BIT(10)),
+       CXL_PMU_EVENT_CXL_ATTR(ddr_pwrdn_entry,                 CXL_PMU_GID_DDR, BIT(11)),
+       CXL_PMU_EVENT_CXL_ATTR(ddr_pwrdn_exit,                  CXL_PMU_GID_DDR, BIT(12)),
+       CXL_PMU_EVENT_CXL_ATTR(ddr_rd_wr_ddr_bus_switching,     CXL_PMU_GID_DDR, BIT(13)),
+       CXL_PMU_EVENT_CXL_ATTR(ddr_incoming_rd_req,             CXL_PMU_GID_DDR, BIT(14)),
+       CXL_PMU_EVENT_CXL_ATTR(ddr_incoming_wr_req,             CXL_PMU_GID_DDR, BIT(15)),
+       /* CXL 4.0 Table 13-5 QUEUE OCCUPANCY events opcodes */
+       CXL_PMU_EVENT_CXL_ATTR(rd_queue_occ,                    CXL_PMU_GID_QUEUE_OCC, BIT(0)),
+       CXL_PMU_EVENT_CXL_ATTR(wr_queue_occ,                    CXL_PMU_GID_QUEUE_OCC, BIT(1)),
+       CXL_PMU_EVENT_CXL_ATTR(rd_wr_merged_queue_occ,          CXL_PMU_GID_QUEUE_OCC, BIT(2)),
+       CXL_PMU_EVENT_CXL_ATTR(pwrdn_event,                     CXL_PMU_GID_QUEUE_OCC, BIT(3)),
+       /* CXL 4.0 Table 13-5 QUEUE RESIDENCY events opcodes */
+       CXL_PMU_EVENT_CXL_ATTR(mc_rd_resid_cnt,                 CXL_PMU_GID_QUEUE_RESID, BIT(0)),
+       CXL_PMU_EVENT_CXL_ATTR(mc_wr_resid_cnt,                 CXL_PMU_GID_QUEUE_RESID, BIT(1)),
+       /* CXL 4.0 Table 13-5 RETRY events opcodes */
+       CXL_PMU_EVENT_CXL_ATTR(retry_event_trig_by_rd_crc,      CXL_PMU_GID_RETRY_EVENTS, BIT(0)),
+       CXL_PMU_EVENT_CXL_ATTR(retry_event_trig_by_wr_crc,      CXL_PMU_GID_RETRY_EVENTS, BIT(1)),
+       CXL_PMU_EVENT_CXL_ATTR(retry_event_trig_by_ca_parity,   CXL_PMU_GID_RETRY_EVENTS, BIT(2)),
+       CXL_PMU_EVENT_CXL_ATTR(retry_event_trig_by_ecc,         CXL_PMU_GID_RETRY_EVENTS, BIT(3)),
+       /* CXL 4.0 Table 13-5 THROTTLE events opcodes */
+       CXL_PMU_EVENT_CXL_ATTR(thermal_throttle_event,          CXL_PMU_GID_THROTTLE, BIT(0)),
+       CXL_PMU_EVENT_CXL_ATTR(power_throttle_event,            CXL_PMU_GID_THROTTLE, BIT(1)),
        NULL
 };