drm/amd/amdgpu: add TAP_DELAYS upload support for gfx10

Support {GLOBAL/SE0/SE1/SE2/SE3}_TAP_DELAYS uploading.

v2: upload TAP_DELAYS before RLC autoload was triggered. (Hawking)

Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 6540582..3ee363b 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -2168,6 +2168,21 @@ static int psp_get_fw_type(struct amdgpu_firmware_info *ucode,
        case AMDGPU_UCODE_ID_RLC_DRAM:
                *type = GFX_FW_TYPE_RLC_DRAM_BOOT;
                break;
+       case AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS:
+               *type = GFX_FW_TYPE_GLOBAL_TAP_DELAYS;
+               break;
+       case AMDGPU_UCODE_ID_SE0_TAP_DELAYS:
+               *type = GFX_FW_TYPE_SE0_TAP_DELAYS;
+               break;
+       case AMDGPU_UCODE_ID_SE1_TAP_DELAYS:
+               *type = GFX_FW_TYPE_SE1_TAP_DELAYS;
+               break;
+       case AMDGPU_UCODE_ID_SE2_TAP_DELAYS:
+               *type = GFX_FW_TYPE_SE2_TAP_DELAYS;
+               break;
+       case AMDGPU_UCODE_ID_SE3_TAP_DELAYS:
+               *type = GFX_FW_TYPE_SE3_TAP_DELAYS;
+               break;
        case AMDGPU_UCODE_ID_SMC:
                *type = GFX_FW_TYPE_SMU;
                break;

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h
index f6fd9e1..03ac36b 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h
@@ -222,6 +222,11 @@ struct amdgpu_rlc {
        u32 rlc_dram_ucode_size_bytes;
        u32 rlcp_ucode_size_bytes;
        u32 rlcv_ucode_size_bytes;
+       u32 global_tap_delays_ucode_size_bytes;
+       u32 se0_tap_delays_ucode_size_bytes;
+       u32 se1_tap_delays_ucode_size_bytes;
+       u32 se2_tap_delays_ucode_size_bytes;
+       u32 se3_tap_delays_ucode_size_bytes;
 
        u32 *register_list_format;
        u32 *register_restore;
@@ -232,6 +237,11 @@ struct amdgpu_rlc {
        u8 *rlc_dram_ucode;
        u8 *rlcp_ucode;
        u8 *rlcv_ucode;
+       u8 *global_tap_delays_ucode;
+       u8 *se0_tap_delays_ucode;
+       u8 *se1_tap_delays_ucode;
+       u8 *se2_tap_delays_ucode;
+       u8 *se3_tap_delays_ucode;
 
        bool is_rlc_v2_1;
 

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
index c312577..939c861 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
@@ -561,6 +561,16 @@ const char *amdgpu_ucode_name(enum AMDGPU_UCODE_ID ucode_id)
                return "RLC_P";
        case AMDGPU_UCODE_ID_RLC_V:
                return "RLC_V";
+       case AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS:
+               return "GLOBAL_TAP_DELAYS";
+       case AMDGPU_UCODE_ID_SE0_TAP_DELAYS:
+               return "SE0_TAP_DELAYS";
+       case AMDGPU_UCODE_ID_SE1_TAP_DELAYS:
+               return "SE1_TAP_DELAYS";
+       case AMDGPU_UCODE_ID_SE2_TAP_DELAYS:
+               return "SE2_TAP_DELAYS";
+       case AMDGPU_UCODE_ID_SE3_TAP_DELAYS:
+               return "SE3_TAP_DELAYS";
        case AMDGPU_UCODE_ID_IMU_I:
                return "IMU_I";
        case AMDGPU_UCODE_ID_IMU_D:
@@ -745,6 +755,26 @@ static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev,
                        ucode->ucode_size = adev->gfx.rlc.rlcv_ucode_size_bytes;
                        ucode_addr = adev->gfx.rlc.rlcv_ucode;
                        break;
+               case AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS:
+                       ucode->ucode_size = adev->gfx.rlc.global_tap_delays_ucode_size_bytes;
+                       ucode_addr = adev->gfx.rlc.global_tap_delays_ucode;
+                       break;
+               case AMDGPU_UCODE_ID_SE0_TAP_DELAYS:
+                       ucode->ucode_size = adev->gfx.rlc.se0_tap_delays_ucode_size_bytes;
+                       ucode_addr = adev->gfx.rlc.se0_tap_delays_ucode;
+                       break;
+               case AMDGPU_UCODE_ID_SE1_TAP_DELAYS:
+                       ucode->ucode_size = adev->gfx.rlc.se1_tap_delays_ucode_size_bytes;
+                       ucode_addr = adev->gfx.rlc.se1_tap_delays_ucode;
+                       break;
+               case AMDGPU_UCODE_ID_SE2_TAP_DELAYS:
+                       ucode->ucode_size = adev->gfx.rlc.se2_tap_delays_ucode_size_bytes;
+                       ucode_addr = adev->gfx.rlc.se2_tap_delays_ucode;
+                       break;
+               case AMDGPU_UCODE_ID_SE3_TAP_DELAYS:
+                       ucode->ucode_size = adev->gfx.rlc.se3_tap_delays_ucode_size_bytes;
+                       ucode_addr = adev->gfx.rlc.se3_tap_delays_ucode;
+                       break;
                case AMDGPU_UCODE_ID_CP_MES:
                        ucode->ucode_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes);
                        ucode_addr = (u8 *)ucode->fw->data +

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
index f510b6a..ebed3f5 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
@@ -266,6 +266,21 @@ struct rlc_firmware_header_v2_3 {
     uint32_t rlcv_ucode_offset_bytes;
 };
 
+/* version_major=2, version_minor=4 */
+struct rlc_firmware_header_v2_4 {
+    struct rlc_firmware_header_v2_3 v2_3;
+    uint32_t global_tap_delays_ucode_size_bytes;
+    uint32_t global_tap_delays_ucode_offset_bytes;
+    uint32_t se0_tap_delays_ucode_size_bytes;
+    uint32_t se0_tap_delays_ucode_offset_bytes;
+    uint32_t se1_tap_delays_ucode_size_bytes;
+    uint32_t se1_tap_delays_ucode_offset_bytes;
+    uint32_t se2_tap_delays_ucode_size_bytes;
+    uint32_t se2_tap_delays_ucode_offset_bytes;
+    uint32_t se3_tap_delays_ucode_size_bytes;
+    uint32_t se3_tap_delays_ucode_offset_bytes;
+};
+
 /* version_major=1, version_minor=0 */
 struct sdma_firmware_header_v1_0 {
        struct common_firmware_header header;
@@ -426,6 +441,11 @@ enum AMDGPU_UCODE_ID {
        AMDGPU_UCODE_ID_CP_MES1_DATA,
        AMDGPU_UCODE_ID_IMU_I,
        AMDGPU_UCODE_ID_IMU_D,
+       AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS,
+       AMDGPU_UCODE_ID_SE0_TAP_DELAYS,
+       AMDGPU_UCODE_ID_SE1_TAP_DELAYS,
+       AMDGPU_UCODE_ID_SE2_TAP_DELAYS,
+       AMDGPU_UCODE_ID_SE3_TAP_DELAYS,
        AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL,
        AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM,
        AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM,

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 5820c3f..fafbad3 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -3976,6 +3976,23 @@ static void gfx_v10_0_init_rlc_iram_dram_microcode(struct amdgpu_device *adev)
        adev->gfx.rlc.rlc_dram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_dram_ucode_offset_bytes);
 }
 
+static void gfx_v10_0_init_tap_delays_microcode(struct amdgpu_device *adev)
+{
+       const struct rlc_firmware_header_v2_4 *rlc_hdr;
+
+       rlc_hdr = (const struct rlc_firmware_header_v2_4 *)adev->gfx.rlc_fw->data;
+       adev->gfx.rlc.global_tap_delays_ucode_size_bytes = le32_to_cpu(rlc_hdr->global_tap_delays_ucode_size_bytes);
+       adev->gfx.rlc.global_tap_delays_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->global_tap_delays_ucode_offset_bytes);
+       adev->gfx.rlc.se0_tap_delays_ucode_size_bytes = le32_to_cpu(rlc_hdr->se0_tap_delays_ucode_size_bytes);
+       adev->gfx.rlc.se0_tap_delays_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->se0_tap_delays_ucode_offset_bytes);
+       adev->gfx.rlc.se1_tap_delays_ucode_size_bytes = le32_to_cpu(rlc_hdr->se1_tap_delays_ucode_size_bytes);
+       adev->gfx.rlc.se1_tap_delays_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->se1_tap_delays_ucode_offset_bytes);
+       adev->gfx.rlc.se2_tap_delays_ucode_size_bytes = le32_to_cpu(rlc_hdr->se2_tap_delays_ucode_size_bytes);
+       adev->gfx.rlc.se2_tap_delays_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->se2_tap_delays_ucode_offset_bytes);
+       adev->gfx.rlc.se3_tap_delays_ucode_size_bytes = le32_to_cpu(rlc_hdr->se3_tap_delays_ucode_size_bytes);
+       adev->gfx.rlc.se3_tap_delays_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->se3_tap_delays_ucode_offset_bytes);
+}
+
 static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev)
 {
        bool ret = false;
@@ -4153,8 +4170,11 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
                if (version_major == 2) {
                        if (version_minor >= 1)
                                gfx_v10_0_init_rlc_ext_microcode(adev);
-                       if (version_minor == 2)
+                       if (version_minor >= 2)
                                gfx_v10_0_init_rlc_iram_dram_microcode(adev);
+                       if (version_minor == 4) {
+                               gfx_v10_0_init_tap_delays_microcode(adev);
+                       }
                }
        }
 
@@ -4251,8 +4271,39 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
                                adev->firmware.fw_size +=
                                        ALIGN(adev->gfx.rlc.rlc_dram_ucode_size_bytes, PAGE_SIZE);
                        }
+
                }
 
+               info = &adev->firmware.ucode[AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS];
+               info->ucode_id = AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS;
+               info->fw = adev->gfx.rlc_fw;
+               adev->firmware.fw_size +=
+                       ALIGN(adev->gfx.rlc.global_tap_delays_ucode_size_bytes, PAGE_SIZE);
+
+               info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SE0_TAP_DELAYS];
+               info->ucode_id = AMDGPU_UCODE_ID_SE0_TAP_DELAYS;
+               info->fw = adev->gfx.rlc_fw;
+               adev->firmware.fw_size +=
+                       ALIGN(adev->gfx.rlc.se0_tap_delays_ucode_size_bytes, PAGE_SIZE);
+
+               info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SE1_TAP_DELAYS];
+               info->ucode_id = AMDGPU_UCODE_ID_SE1_TAP_DELAYS;
+               info->fw = adev->gfx.rlc_fw;
+               adev->firmware.fw_size +=
+                       ALIGN(adev->gfx.rlc.se1_tap_delays_ucode_size_bytes, PAGE_SIZE);
+
+               info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SE2_TAP_DELAYS];
+               info->ucode_id = AMDGPU_UCODE_ID_SE2_TAP_DELAYS;
+               info->fw = adev->gfx.rlc_fw;
+               adev->firmware.fw_size +=
+                       ALIGN(adev->gfx.rlc.se2_tap_delays_ucode_size_bytes, PAGE_SIZE);
+
+               info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SE3_TAP_DELAYS];
+               info->ucode_id = AMDGPU_UCODE_ID_SE3_TAP_DELAYS;
+               info->fw = adev->gfx.rlc_fw;
+               adev->firmware.fw_size +=
+                       ALIGN(adev->gfx.rlc.se3_tap_delays_ucode_size_bytes, PAGE_SIZE);
+
                info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
                info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
                info->fw = adev->gfx.mec_fw;

diff --git a/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h b/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h
index 236b7a6..22c775f 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h
+++ b/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h
@@ -259,6 +259,8 @@ enum psp_gfx_fw_type {
        GFX_FW_TYPE_SDMA7                           = 57,   /* SDMA7                    MI      */
        GFX_FW_TYPE_VCN1                            = 58,   /* VCN1                     MI      */
        GFX_FW_TYPE_CAP                             = 62,   /* CAP_FW                           */
+       GFX_FW_TYPE_SE2_TAP_DELAYS                  = 65,   /* SE2 TAP DELAYS           NV      */
+       GFX_FW_TYPE_SE3_TAP_DELAYS                  = 66,   /* SE3 TAP DELAYS           NV      */
        GFX_FW_TYPE_REG_LIST                        = 67,   /* REG_LIST                 MI      */
        GFX_FW_TYPE_IMU_I                           = 68,   /* IMU Instruction FW       SOC21   */
        GFX_FW_TYPE_IMU_D                           = 69,   /* IMU Data FW              SOC21   */