drm/i915/icl: Define DSI mode ctl register

This patch defines DSI IO mode control register and it's bits
used while enabling IO power for DSI.

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1530798591-2077-4-git-send-email-madhav.chauhan@intel.com

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a35f414..eb3b754 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9688,6 +9688,14 @@ enum skl_power_gate {
 #define _BXT_MIPIC_PORT_CTRL                           0x6B8C0
 #define BXT_MIPI_PORT_CTRL(tc) _MMIO_MIPI(tc, _BXT_MIPIA_PORT_CTRL, _BXT_MIPIC_PORT_CTRL)
 
+/* ICL DSI MODE control */
+#define _ICL_DSI_IO_MODECTL_0                          0x6B094
+#define _ICL_DSI_IO_MODECTL_1                          0x6B894
+#define ICL_DSI_IO_MODECTL(port)       _MMIO_PORT(port,        \
+                                                   _ICL_DSI_IO_MODECTL_0, \
+                                                   _ICL_DSI_IO_MODECTL_1)
+#define  COMBO_PHY_MODE_DSI                            (1 << 0)
+
 #define BXT_P_DSI_REGULATOR_CFG                        _MMIO(0x160020)
 #define  STAP_SELECT                                   (1 << 0)