arm64: dts: renesas: r8a779h0: Add L3 cache controller

Describe the cache configuration for the first Cortex-A76 CPU core on
the Renesas R-Car V4M (R8A779H0) SoC.

Signed-off-by: Duy Nguyen <duy.nguyen.rh@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/9d56a46892c5e0957d244370e6809013cf815905.1706796979.git.geert+renesas@glider.be

diff --git a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi
index eb555cb..f476951 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi
@@ -23,6 +23,14 @@
                        reg = <0>;
                        device_type = "cpu";
                        power-domains = <&sysc R8A779H0_PD_A1E0D0C0>;
+                       next-level-cache = <&L3_CA76>;
+               };
+
+               L3_CA76: cache-controller {
+                       compatible = "cache";
+                       power-domains = <&sysc R8A779H0_PD_A2E0D0>;
+                       cache-unified;
+                       cache-level = <3>;
                };
        };