drm/amd/display: Wait for DMCUB to finish loading before executing commands

[Why]
When we execute the first command for ASIC_INIT for command table
offloading we can hit a timing scenario such that the interrupts
for the inbox wptr haven't been enabled yet and the first command
is ignored until the second command is sent.

[How]
This happens when either the SCRATCH0 is already the correct status
code or autoload check is unsupported.

Clear SCRATCH0 during reset.

Also ensure that we don't accidentally reset the ASIC again in case
of a hang by clearing GPINT while we're at it.

Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Chris Park <Chris.Park@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
index 993e47e..63bb9e2 100644 (file)
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
@@ -116,6 +116,10 @@ void dmub_dcn20_reset(struct dmub_srv *dmub)
                                break;
                }
 
+               /* Clear the GPINT command manually so we don't reset again. */
+               cmd.all = 0;
+               dmub->hw_funcs.set_gpint(dmub, cmd);
+
                /* Force reset in case we timed out, DMCUB is likely hung. */
        }
 
@@ -124,6 +128,7 @@ void dmub_dcn20_reset(struct dmub_srv *dmub)
        REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 1);
        REG_WRITE(DMCUB_INBOX1_RPTR, 0);
        REG_WRITE(DMCUB_INBOX1_WPTR, 0);
+       REG_WRITE(DMCUB_SCRATCH0, 0);
 }
 
 void dmub_dcn20_reset_release(struct dmub_srv *dmub)