clk: qcom: gcc-x1e80100: Set FORCE MEM CORE for UFS clocks

Update the force mem core bit for UFS ICE clock and UFS PHY AXI clock to
force the core on signal to remain active during halt state of the clk.
If force mem core bit of the clock is not set, the memories of the
subsystem will not retain the logic across power states. This is
required for the MCQ feature of UFS.

Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Reviewed-by: Imran Shaik <quic_imrashai@quicinc.com>
Link: https://lore.kernel.org/r/20250414-gcc_ufs_mem_core-v1-2-67b5529b9b5d@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/drivers/clk/qcom/gcc-x1e80100.c b/drivers/clk/qcom/gcc-x1e80100.c
index 009f391..3e44757 100644 (file)
--- a/drivers/clk/qcom/gcc-x1e80100.c
+++ b/drivers/clk/qcom/gcc-x1e80100.c
@@ -6753,6 +6753,10 @@ static int gcc_x1e80100_probe(struct platform_device *pdev)
        /* Clear GDSC_SLEEP_ENA_VOTE to stop votes being auto-removed in sleep. */
        regmap_write(regmap, 0x52224, 0x0);
 
+       /* FORCE_MEM_CORE_ON for ufs phy ice core and gcc ufs phy axi clocks  */
+       qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true);
+       qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_axi_clk, true);
+
        return qcom_cc_really_probe(&pdev->dev, &gcc_x1e80100_desc, regmap);
 }