drm/xe: Don't hardcode GuC's MOCS index in register header

Although PVC is currently the only platform that needs us to program a
GuC register with the index of an uncached MOCS entry, it's likely other
platforms will need this in the future.  Rather than hardcoding PVC's
index into the register header, we should just pull the appropriate
index from gt->mocs.uc_index to future-proof the code.

Reviewed-by: Matthew Brost <matthew.brost@intel.com>
Link: https://lore.kernel.org/r/20230602235210.1314028-3-matthew.d.roper@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

diff --git a/drivers/gpu/drm/xe/regs/xe_guc_regs.h b/drivers/gpu/drm/xe/regs/xe_guc_regs.h
index ea8118f..fcb7472 100644 (file)
--- a/drivers/gpu/drm/xe/regs/xe_guc_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_guc_regs.h
@@ -45,10 +45,7 @@
 #define   GUC_WOPCM_SIZE_LOCKED                        REG_BIT(0)
 
 #define GUC_SHIM_CONTROL                       XE_REG(0xc064)
-#define   PVC_GUC_MOCS_INDEX_MASK              REG_GENMASK(25, 24)
-#define   PVC_GUC_MOCS_UC_INDEX                        1
-#define   PVC_GUC_MOCS_INDEX(index)            REG_FIELD_PREP(PVC_GUC_MOCS_INDEX_MASK, \
-                                                              index)
+#define   GUC_MOCS_INDEX_MASK                  REG_GENMASK(25, 24)
 #define   GUC_SHIM_WC_ENABLE                   REG_BIT(21)
 #define   GUC_ENABLE_MIA_CLOCK_GATING          REG_BIT(15)
 #define   GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA REG_BIT(10)

diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
index 04a57af..e51d8fb 100644 (file)
--- a/drivers/gpu/drm/xe/xe_guc.c
+++ b/drivers/gpu/drm/xe/xe_guc.c
@@ -328,7 +328,7 @@ static void guc_prepare_xfer(struct xe_guc *guc)
                                GUC_ENABLE_MIA_CACHING;
 
        if (xe->info.platform == XE_PVC)
-               shim_flags |= PVC_GUC_MOCS_INDEX(PVC_GUC_MOCS_UC_INDEX);
+               shim_flags |= REG_FIELD_PREP(GUC_MOCS_INDEX_MASK, gt->mocs.uc_index);
 
        /* Must program this register before loading the ucode with DMA */
        xe_mmio_write32(gt, GUC_SHIM_CONTROL, shim_flags);