mfd: lpc_ich: Move APL GPIO resources to a custom structure
authorAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Tue, 26 Sep 2023 19:08:33 +0000 (22:08 +0300)
committerLee Jones <lee@kernel.org>
Wed, 1 Nov 2023 10:02:13 +0000 (10:02 +0000)
We are expecting more platforms that want to instantiate
the GPIO device via P2SB. For them prepare the custom structure
and move Apollo Lake data there. Refactor the code accordingly.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20230926190834.932233-3-andriy.shevchenko@linux.intel.com
Signed-off-by: Lee Jones <lee@kernel.org>
drivers/mfd/lpc_ich.c
include/linux/mfd/lpc_ich.h

index 58da6c9..8b21d0f 100644 (file)
@@ -131,22 +131,33 @@ static struct mfd_cell lpc_ich_gpio_cell = {
        .ignore_resource_conflicts = true,
 };
 
+#define INTEL_GPIO_RESOURCE_SIZE       0x1000
+
+struct lpc_ich_gpio_info {
+       const char *hid;
+       const struct mfd_cell *devices;
+       size_t nr_devices;
+       struct resource **resources;
+       size_t nr_resources;
+       resource_size_t *offsets;
+};
+
 #define APL_GPIO_NORTH         0
 #define APL_GPIO_NORTHWEST     1
 #define APL_GPIO_WEST          2
 #define APL_GPIO_SOUTHWEST     3
+
 #define APL_GPIO_NR_DEVICES    4
+#define APL_GPIO_NR_RESOURCES  4
 
 /* Offset data for Apollo Lake GPIO controllers */
-static resource_size_t apl_gpio_offsets[APL_GPIO_NR_DEVICES] = {
+static resource_size_t apl_gpio_offsets[APL_GPIO_NR_RESOURCES] = {
        [APL_GPIO_NORTH]        = 0xc50000,
        [APL_GPIO_NORTHWEST]    = 0xc40000,
        [APL_GPIO_WEST]         = 0xc70000,
        [APL_GPIO_SOUTHWEST]    = 0xc00000,
 };
 
-#define APL_GPIO_RESOURCE_SIZE         0x1000
-
 #define APL_GPIO_IRQ                   14
 
 static struct resource apl_gpio_resources[APL_GPIO_NR_DEVICES][2] = {
@@ -168,6 +179,13 @@ static struct resource apl_gpio_resources[APL_GPIO_NR_DEVICES][2] = {
        },
 };
 
+static struct resource *apl_gpio_mem_resources[APL_GPIO_NR_RESOURCES] = {
+       [APL_GPIO_NORTH] = &apl_gpio_resources[APL_GPIO_NORTH][0],
+       [APL_GPIO_NORTHWEST] = &apl_gpio_resources[APL_GPIO_NORTHWEST][0],
+       [APL_GPIO_WEST] = &apl_gpio_resources[APL_GPIO_WEST][0],
+       [APL_GPIO_SOUTHWEST] = &apl_gpio_resources[APL_GPIO_SOUTHWEST][0],
+};
+
 static const struct mfd_cell apl_gpio_devices[APL_GPIO_NR_DEVICES] = {
        [APL_GPIO_NORTH] = {
                .name = "apollolake-pinctrl",
@@ -199,6 +217,15 @@ static const struct mfd_cell apl_gpio_devices[APL_GPIO_NR_DEVICES] = {
        },
 };
 
+static const struct lpc_ich_gpio_info apl_gpio_info = {
+       .hid = "INT3452",
+       .devices = apl_gpio_devices,
+       .nr_devices = ARRAY_SIZE(apl_gpio_devices),
+       .resources = apl_gpio_mem_resources,
+       .nr_resources = ARRAY_SIZE(apl_gpio_mem_resources),
+       .offsets = apl_gpio_offsets,
+};
+
 static struct mfd_cell lpc_ich_spi_cell = {
        .name = "intel-spi",
        .num_resources = ARRAY_SIZE(intel_spi_res),
@@ -618,6 +645,7 @@ static struct lpc_ich_info lpc_chipset_info[] = {
        [LPC_APL] = {
                .name = "Apollo Lake SoC",
                .iTCO_version = 5,
+               .gpio_info = &apl_gpio_info,
                .spi_type = INTEL_SPI_BXT,
        },
        [LPC_GLK] = {
@@ -1156,30 +1184,32 @@ wdt_done:
 
 static int lpc_ich_init_pinctrl(struct pci_dev *dev)
 {
+       struct lpc_ich_priv *priv = pci_get_drvdata(dev);
+       const struct lpc_ich_gpio_info *info = lpc_chipset_info[priv->chipset].gpio_info;
        struct resource base;
        unsigned int i;
        int ret;
 
        /* Check, if GPIO has been exported as an ACPI device */
-       if (acpi_dev_present("INT3452", NULL, -1))
+       if (acpi_dev_present(info->hid, NULL, -1))
                return -EEXIST;
 
        ret = p2sb_bar(dev->bus, 0, &base);
        if (ret)
                return ret;
 
-       for (i = 0; i < ARRAY_SIZE(apl_gpio_devices); i++) {
-               struct resource *mem = &apl_gpio_resources[i][0];
-               resource_size_t offset = apl_gpio_offsets[i];
+       for (i = 0; i < info->nr_resources; i++) {
+               struct resource *mem = info->resources[i];
+               resource_size_t offset = info->offsets[i];
 
                /* Fill MEM resource */
                mem->start = base.start + offset;
-               mem->end = base.start + offset + APL_GPIO_RESOURCE_SIZE - 1;
+               mem->end = base.start + offset + INTEL_GPIO_RESOURCE_SIZE - 1;
                mem->flags = base.flags;
        }
 
-       return mfd_add_devices(&dev->dev, 0, apl_gpio_devices,
-                              ARRAY_SIZE(apl_gpio_devices), NULL, 0, NULL);
+       return mfd_add_devices(&dev->dev, 0, info->devices, info->nr_devices,
+                              NULL, 0, NULL);
 }
 
 static bool lpc_ich_byt_set_writeable(void __iomem *base, void *data)
@@ -1332,7 +1362,7 @@ static int lpc_ich_probe(struct pci_dev *dev,
                        cell_added = true;
        }
 
-       if (priv->chipset == LPC_APL) {
+       if (lpc_chipset_info[priv->chipset].gpio_info) {
                ret = lpc_ich_init_pinctrl(dev);
                if (!ret)
                        cell_added = true;
index 83621e0..1fbda1f 100644 (file)
@@ -26,11 +26,14 @@ enum lpc_gpio_versions {
        AVOTON_GPIO,
 };
 
+struct lpc_ich_gpio_info;
+
 struct lpc_ich_info {
        char name[32];
        unsigned int iTCO_version;
        enum lpc_gpio_versions gpio_version;
        enum intel_spi_type spi_type;
+       const struct lpc_ich_gpio_info *gpio_info;
        u8 use_gpio;
 };