drm/amd/display: Fix dpstreamclk programming

[WHY]
Currently programming incorrect hpo inst as well as selecting incorrect source

[HOW]
Use hpo inst instead of otg inst to select dpstreamclk inst

Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Michael Strauss <michael.strauss@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
index 799a383..7f34418 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
@@ -158,9 +158,11 @@ static void dccg31_disable_dpstreamclk(struct dccg *dccg, int otg_inst)
        }
 }
 
-void dccg31_set_dpstreamclk(struct dccg *dccg,
-                           enum streamclk_source src,
-                           int otg_inst)
+void dccg31_set_dpstreamclk(
+               struct dccg *dccg,
+               enum streamclk_source src,
+               int otg_inst,
+               int dp_hpo_inst)
 {
        if (src == REFCLK)
                dccg31_disable_dpstreamclk(dccg, otg_inst);

diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h
index 32b5593..0902ce5 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h
@@ -161,11 +161,6 @@ struct dccg *dccg31_create(
 
 void dccg31_init(struct dccg *dccg);
 
-void dccg31_set_dpstreamclk(
-               struct dccg *dccg,
-               enum streamclk_source src,
-               int otg_inst);
-
 void dccg31_enable_symclk32_se(
                struct dccg *dccg,
                int hpo_se_inst,
@@ -207,7 +202,8 @@ void dccg31_get_dccg_ref_freq(
 void dccg31_set_dpstreamclk(
        struct dccg *dccg,
        enum streamclk_source src,
-       int otg_inst);
+       int otg_inst,
+       int dp_hpo_inst);
 
 void dccg31_set_dtbclk_dto(
                struct dccg *dccg,

diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dccg.c
index 3852a6d..232cc15 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dccg.c
@@ -184,7 +184,8 @@ void dccg314_set_dtbclk_dto(
 void dccg314_set_dpstreamclk(
                struct dccg *dccg,
                enum streamclk_source src,
-               int otg_inst)
+               int otg_inst,
+               int dp_hpo_inst)
 {
        struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
 
@@ -192,26 +193,26 @@ void dccg314_set_dpstreamclk(
        dccg314_set_dtbclk_p_src(dccg, src, otg_inst);
 
        /* enabled to select one of the DTBCLKs for pipe */
-       switch (otg_inst) {
+       switch (dp_hpo_inst) {
        case 0:
                REG_UPDATE_2(DPSTREAMCLK_CNTL,
                                        DPSTREAMCLK0_EN, (src == REFCLK) ? 0 : 1,
-                                       DPSTREAMCLK0_SRC_SEL, 0);
+                                       DPSTREAMCLK0_SRC_SEL, otg_inst);
                break;
        case 1:
                REG_UPDATE_2(DPSTREAMCLK_CNTL,
                                        DPSTREAMCLK1_EN, (src == REFCLK) ? 0 : 1,
-                                       DPSTREAMCLK1_SRC_SEL, 1);
+                                       DPSTREAMCLK1_SRC_SEL, otg_inst);
                break;
        case 2:
                REG_UPDATE_2(DPSTREAMCLK_CNTL,
                                        DPSTREAMCLK2_EN, (src == REFCLK) ? 0 : 1,
-                                       DPSTREAMCLK2_SRC_SEL, 2);
+                                       DPSTREAMCLK2_SRC_SEL, otg_inst);
                break;
        case 3:
                REG_UPDATE_2(DPSTREAMCLK_CNTL,
                                        DPSTREAMCLK3_EN, (src == REFCLK) ? 0 : 1,
-                                       DPSTREAMCLK3_SRC_SEL, 3);
+                                       DPSTREAMCLK3_SRC_SEL, otg_inst);
                break;
        default:
                BREAK_TO_DEBUGGER();

diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c
index 12fc3af..a31c64b 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c
@@ -211,7 +211,8 @@ static void dccg32_get_dccg_ref_freq(struct dccg *dccg,
 void dccg32_set_dpstreamclk(
                struct dccg *dccg,
                enum streamclk_source src,
-               int otg_inst)
+               int otg_inst,
+               int dp_hpo_inst)
 {
        struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
 

diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
index c2d116c..ce00676 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
@@ -101,7 +101,8 @@ struct dccg_funcs {
        void (*set_dpstreamclk)(
                        struct dccg *dccg,
                        enum streamclk_source src,
-                       int otg_inst);
+                       int otg_inst,
+                       int dp_hpo_inst);
 
        void (*enable_symclk32_se)(
                        struct dccg *dccg,

diff --git a/drivers/gpu/drm/amd/display/dc/link/link_hwss_hpo_dp.c b/drivers/gpu/drm/amd/display/dc/link/link_hwss_hpo_dp.c
index ea6cf8b..db7b0b1 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/link/link_hwss_hpo_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/link/link_hwss_hpo_dp.c
@@ -116,7 +116,7 @@ static void setup_hpo_dp_stream_encoder(struct pipe_ctx *pipe_ctx)
        dto_params.timing = &pipe_ctx->stream->timing;
        dto_params.ref_dtbclk_khz = dc->clk_mgr->funcs->get_dtb_ref_clk_frequency(dc->clk_mgr);
 
-       dccg->funcs->set_dpstreamclk(dccg, DTBCLK0, tg->inst);
+       dccg->funcs->set_dpstreamclk(dccg, DTBCLK0, tg->inst, link_enc->inst);
        dccg->funcs->enable_symclk32_se(dccg, stream_enc->inst, phyd32clk);
        dccg->funcs->set_dtbclk_dto(dccg, &dto_params);
        stream_enc->funcs->enable_stream(stream_enc);
@@ -137,7 +137,7 @@ static void reset_hpo_dp_stream_encoder(struct pipe_ctx *pipe_ctx)
        stream_enc->funcs->disable(stream_enc);
        dccg->funcs->set_dtbclk_dto(dccg, &dto_params);
        dccg->funcs->disable_symclk32_se(dccg, stream_enc->inst);
-       dccg->funcs->set_dpstreamclk(dccg, REFCLK, tg->inst);
+       dccg->funcs->set_dpstreamclk(dccg, REFCLK, tg->inst,  pipe_ctx->link_res.hpo_dp_link_enc->inst);
 }
 
 static void setup_hpo_dp_stream_attribute(struct pipe_ctx *pipe_ctx)