soc/tegra: fuse: Add Tegra234 support
authorThierry Reding <treding@nvidia.com>
Thu, 17 Sep 2020 10:07:47 +0000 (12:07 +0200)
committerThierry Reding <treding@nvidia.com>
Fri, 18 Sep 2020 13:55:29 +0000 (15:55 +0200)
Add support for FUSE block found on the Tegra234 SoC, which is largely
similar to the IP found on previous generations.

Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
drivers/soc/tegra/fuse/fuse-tegra.c
drivers/soc/tegra/fuse/fuse-tegra30.c
drivers/soc/tegra/fuse/fuse.h
drivers/soc/tegra/fuse/tegra-apbmisc.c
include/soc/tegra/fuse.h

index 7e6b6ee..94b60a6 100644 (file)
@@ -49,6 +49,9 @@ static struct tegra_fuse *fuse = &(struct tegra_fuse) {
 };
 
 static const struct of_device_id tegra_fuse_match[] = {
+#ifdef CONFIG_ARCH_TEGRA_234_SOC
+       { .compatible = "nvidia,tegra234-efuse", .data = &tegra234_fuse_soc },
+#endif
 #ifdef CONFIG_ARCH_TEGRA_194_SOC
        { .compatible = "nvidia,tegra194-efuse", .data = &tegra194_fuse_soc },
 #endif
@@ -326,7 +329,8 @@ const struct attribute_group tegra_soc_attr_group = {
        .attrs = tegra_soc_attr,
 };
 
-#ifdef CONFIG_ARCH_TEGRA_194_SOC
+#if IS_ENABLED(CONFIG_ARCH_TEGRA_194_SOC) || \
+    IS_ENABLED(CONFIG_ARCH_TEGRA_234_SOC)
 static ssize_t platform_show(struct device *dev, struct device_attribute *attr,
                             char *buf)
 {
index 85accef..9ea7f01 100644 (file)
@@ -356,3 +356,33 @@ const struct tegra_fuse_soc tegra194_fuse_soc = {
        .soc_attr_group = &tegra194_soc_attr_group,
 };
 #endif
+
+#if defined(CONFIG_ARCH_TEGRA_234_SOC)
+static const struct nvmem_cell_lookup tegra234_fuse_lookups[] = {
+       {
+               .nvmem_name = "fuse",
+               .cell_name = "xusb-pad-calibration",
+               .dev_id = "3520000.padctl",
+               .con_id = "calibration",
+       }, {
+               .nvmem_name = "fuse",
+               .cell_name = "xusb-pad-calibration-ext",
+               .dev_id = "3520000.padctl",
+               .con_id = "calibration-ext",
+       },
+};
+
+static const struct tegra_fuse_info tegra234_fuse_info = {
+       .read = tegra30_fuse_read,
+       .size = 0x300,
+       .spare = 0x280,
+};
+
+const struct tegra_fuse_soc tegra234_fuse_soc = {
+       .init = tegra30_fuse_init,
+       .info = &tegra234_fuse_info,
+       .lookups = tegra234_fuse_lookups,
+       .num_lookups = ARRAY_SIZE(tegra234_fuse_lookups),
+       .soc_attr_group = &tegra194_soc_attr_group,
+};
+#endif
index 9d4fc31..e057a58 100644 (file)
@@ -115,9 +115,17 @@ extern const struct tegra_fuse_soc tegra210_fuse_soc;
 extern const struct tegra_fuse_soc tegra186_fuse_soc;
 #endif
 
+#if IS_ENABLED(CONFIG_ARCH_TEGRA_194_SOC) || \
+    IS_ENABLED(CONFIG_ARCH_TEGRA_234_SOC)
+extern const struct attribute_group tegra194_soc_attr_group;
+#endif
+
 #ifdef CONFIG_ARCH_TEGRA_194_SOC
 extern const struct tegra_fuse_soc tegra194_fuse_soc;
-extern const struct attribute_group tegra194_soc_attr_group;
+#endif
+
+#ifdef CONFIG_ARCH_TEGRA_234_SOC
+extern const struct tegra_fuse_soc tegra234_fuse_soc;
 #endif
 
 #endif
index 946a2d9..0e4eb26 100644 (file)
@@ -56,6 +56,7 @@ bool tegra_is_silicon(void)
 {
        switch (tegra_get_chip_id()) {
        case TEGRA194:
+       case TEGRA234:
                if (tegra_get_platform() == 0)
                        return true;
 
index a9db917..c702bd2 100644 (file)
@@ -14,6 +14,7 @@
 #define TEGRA210       0x21
 #define TEGRA186       0x18
 #define TEGRA194       0x19
+#define TEGRA234       0x23
 
 #define TEGRA_FUSE_SKU_CALIB_0 0xf0
 #define TEGRA30_FUSE_SATA_CALIB        0x124