{
struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
- if (!dai->active) {
+ if (!snd_soc_dai_active(dai)) {
/* Set synchronous mode */
regmap_update_bits(esai_priv->regmap, REG_ESAI_SAICR,
ESAI_SAICR_SYNC, esai_priv->synchronous ?
int ret;
/* Reset module and interrupts only for first initialization */
- if (!cpu_dai->active) {
+ if (!snd_soc_dai_active(cpu_dai)) {
ret = clk_prepare_enable(spdif_priv->coreclk);
if (ret) {
dev_err(&pdev->dev, "failed to enable core clock\n");
regmap_update_bits(regmap, REG_SPDIF_SCR, mask, scr);
/* Power down SPDIF module only if tx&rx are both inactive */
- if (!cpu_dai->active) {
+ if (!snd_soc_dai_active(cpu_dai)) {
spdif_intr_status_clear(spdif_priv);
regmap_update_bits(regmap, REG_SPDIF_SCR,
SCR_LOW_POWER, SCR_LOW_POWER);