drm/amdgpu: remove unnecessary logic of ASIC check

Remove some unused ASIC check logic.
Remove some definition of amdgpu_device which only used by
the removed ASIC check logic.(V2)

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index b8b4cff..a6170a3 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -7683,14 +7683,9 @@ static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
 static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
                                     u64 seq, unsigned flags)
 {
-       struct amdgpu_device *adev = ring->adev;
        bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
        bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
 
-       /* Interrupt not work fine on GFX10.1 model yet. Use fallback instead */
-       if (adev->pdev->device == 0x50)
-               int_sel = false;
-
        /* RELEASE_MEM - flush caches, send int */
        amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
        amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ |

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
index 1baeddf..abb0ab6 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
@@ -485,7 +485,6 @@ static void sdma_v5_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 static void sdma_v5_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
                                      unsigned flags)
 {
-       struct amdgpu_device *adev = ring->adev;
        bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
        /* write the fence */
        amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
@@ -508,8 +507,7 @@ static void sdma_v5_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 se
                amdgpu_ring_write(ring, upper_32_bits(seq));
        }
 
-       /* Interrupt not work fine on GFX10.1 model yet. Use fallback instead */
-       if ((flags & AMDGPU_FENCE_FLAG_INT) && adev->pdev->device != 0x50) {
+       if (flags & AMDGPU_FENCE_FLAG_INT) {
                /* generate an interrupt */
                amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
                amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
@@ -887,10 +885,6 @@ static int sdma_v5_0_start(struct amdgpu_device *adev)
                r = sdma_v5_0_load_microcode(adev);
                if (r)
                        return r;
-
-               /* The value of mmSDMA_F32_CNTL is invalid the moment after loading fw */
-               if (amdgpu_emu_mode == 1 && adev->pdev->device == 0x4d)
-                       msleep(1000);
        }
 
        /* unhalt the MEs */

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
index 4dbc119..1ef14b6 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
@@ -417,7 +417,6 @@ static void sdma_v5_2_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 static void sdma_v5_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
                                      unsigned flags)
 {
-       struct amdgpu_device *adev = ring->adev;
        bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
        /* write the fence */
        amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
@@ -440,8 +439,7 @@ static void sdma_v5_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 se
                amdgpu_ring_write(ring, upper_32_bits(seq));
        }
 
-       /* Interrupt not work fine on GFX10.1 model yet. Use fallback instead */
-       if ((flags & AMDGPU_FENCE_FLAG_INT) && adev->pdev->device != 0x50) {
+       if (flags & AMDGPU_FENCE_FLAG_INT) {
                /* generate an interrupt */
                amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
                amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));