};
 
 static const struct drm_i915_reg_descriptor hsw_render_regs[] = {
+       REG64_IDX(HSW_CS_GPR, 0),
+       REG64_IDX(HSW_CS_GPR, 1),
+       REG64_IDX(HSW_CS_GPR, 2),
+       REG64_IDX(HSW_CS_GPR, 3),
+       REG64_IDX(HSW_CS_GPR, 4),
+       REG64_IDX(HSW_CS_GPR, 5),
+       REG64_IDX(HSW_CS_GPR, 6),
+       REG64_IDX(HSW_CS_GPR, 7),
+       REG64_IDX(HSW_CS_GPR, 8),
+       REG64_IDX(HSW_CS_GPR, 9),
+       REG64_IDX(HSW_CS_GPR, 10),
+       REG64_IDX(HSW_CS_GPR, 11),
+       REG64_IDX(HSW_CS_GPR, 12),
+       REG64_IDX(HSW_CS_GPR, 13),
+       REG64_IDX(HSW_CS_GPR, 14),
+       REG64_IDX(HSW_CS_GPR, 15),
        REG32(HSW_SCRATCH1,
              .mask = ~HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE,
              .value = 0),
 
 #define GEN7_GPGPU_DISPATCHDIMY         _MMIO(0x2504)
 #define GEN7_GPGPU_DISPATCHDIMZ         _MMIO(0x2508)
 
+/* There are the 16 64-bit CS General Purpose Registers */
+#define HSW_CS_GPR(n)                   _MMIO(0x2600 + (n) * 8)
+#define HSW_CS_GPR_UDW(n)               _MMIO(0x2600 + (n) * 8 + 4)
+
 #define OACONTROL _MMIO(0x2360)
 
 #define _GEN7_PIPEA_DE_LOAD_SL 0x70068