ARM: dts: DRA7: add entry for qspi mmap region
authorVignesh R <vigneshr@ti.com>
Fri, 11 Dec 2015 04:09:59 +0000 (09:39 +0530)
committerTony Lindgren <tony@atomide.com>
Fri, 18 Dec 2015 16:40:47 +0000 (08:40 -0800)
Add qspi memory mapped region entries for DRA7xx based SoCs. Also,
update the binding documents for the controller to document this change.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Documentation/devicetree/bindings/spi/ti_qspi.txt
arch/arm/boot/dts/dra7.dtsi

index 601a360..809c3f3 100644 (file)
@@ -15,6 +15,10 @@ Recommended properties:
 - spi-max-frequency: Definition as per
                      Documentation/devicetree/bindings/spi/spi-bus.txt
 
+Optional properties:
+- syscon-chipselects: Handle to system control region contains QSPI
+                     chipselect register and offset of that register.
+
 Example:
 
 qspi: qspi@4b300000 {
@@ -26,3 +30,16 @@ qspi: qspi@4b300000 {
        spi-max-frequency = <25000000>;
        ti,hwmods = "qspi";
 };
+
+For dra7xx:
+qspi: qspi@4b300000 {
+       compatible = "ti,dra7xxx-qspi";
+       reg = <0x4b300000 0x100>,
+             <0x5c000000 0x4000000>,
+       reg-names = "qspi_base", "qspi_mmap";
+       syscon-chipselects = <&scm_conf 0x558>;
+       #address-cells = <1>;
+       #size-cells = <0>;
+       spi-max-frequency = <48000000>;
+       ti,hwmods = "qspi";
+};
index b2badf9..bf5dd1e 100644 (file)
 
                qspi: qspi@4b300000 {
                        compatible = "ti,dra7xxx-qspi";
-                       reg = <0x4b300000 0x100>;
-                       reg-names = "qspi_base";
+                       reg = <0x4b300000 0x100>,
+                             <0x5c000000 0x4000000>;
+                       reg-names = "qspi_base", "qspi_mmap";
+                       syscon-chipselects = <&scm_conf 0x558>;
                        #address-cells = <1>;
                        #size-cells = <0>;
                        ti,hwmods = "qspi";