drm/amd/pm: correct the thermal alert temperature limit settings
authorEvan Quan <evan.quan@amd.com>
Tue, 25 Aug 2020 02:35:11 +0000 (10:35 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 26 Aug 2020 20:40:19 +0000 (16:40 -0400)
Do the maths in celsius degree. This can fix the issues caused
by the changes below:

drm/amd/pm: correct Vega20 swctf limit setting
drm/amd/pm: correct Vega12 swctf limit setting
drm/amd/pm: correct Vega10 swctf limit setting

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c
drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_thermal.c
drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c

index ce9514c..d572ba4 100644 (file)
@@ -367,14 +367,13 @@ static int vega10_thermal_set_temperature_range(struct pp_hwmgr *hwmgr,
                (struct phm_ppt_v2_information *)(hwmgr->pptable);
        struct phm_tdp_table *tdp_table = pp_table_info->tdp_table;
        struct amdgpu_device *adev = hwmgr->adev;
-       int low = VEGA10_THERMAL_MINIMUM_ALERT_TEMP *
-                       PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
-       int high = VEGA10_THERMAL_MAXIMUM_ALERT_TEMP *
-                       PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
+       int low = VEGA10_THERMAL_MINIMUM_ALERT_TEMP;
+       int high = VEGA10_THERMAL_MAXIMUM_ALERT_TEMP;
        uint32_t val;
 
-       if (low < range->min)
-               low = range->min;
+       /* compare them in unit celsius degree */
+       if (low < range->min / PP_TEMPERATURE_UNITS_PER_CENTIGRADES)
+               low = range->min / PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
        if (high > tdp_table->usSoftwareShutdownTemp)
                high = tdp_table->usSoftwareShutdownTemp;
 
@@ -385,8 +384,8 @@ static int vega10_thermal_set_temperature_range(struct pp_hwmgr *hwmgr,
 
        val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
        val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
-       val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));
-       val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));
+       val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, high);
+       val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, low);
        val &= (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK) &
                        (~THM_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK) &
                        (~THM_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK);
index e755fc0..7ace439 100644 (file)
@@ -173,14 +173,13 @@ static int vega12_thermal_set_temperature_range(struct pp_hwmgr *hwmgr,
        struct phm_ppt_v3_information *pptable_information =
                (struct phm_ppt_v3_information *)hwmgr->pptable;
        struct amdgpu_device *adev = hwmgr->adev;
-       int low = VEGA12_THERMAL_MINIMUM_ALERT_TEMP *
-                       PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
-       int high = VEGA12_THERMAL_MAXIMUM_ALERT_TEMP *
-                       PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
+       int low = VEGA12_THERMAL_MINIMUM_ALERT_TEMP;
+       int high = VEGA12_THERMAL_MAXIMUM_ALERT_TEMP;
        uint32_t val;
 
-       if (low < range->min)
-               low = range->min;
+       /* compare them in unit celsius degree */
+       if (low < range->min / PP_TEMPERATURE_UNITS_PER_CENTIGRADES)
+               low = range->min / PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
        if (high > pptable_information->us_software_shutdown_temp)
                high = pptable_information->us_software_shutdown_temp;
 
@@ -191,8 +190,8 @@ static int vega12_thermal_set_temperature_range(struct pp_hwmgr *hwmgr,
 
        val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
        val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
-       val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));
-       val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));
+       val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, high);
+       val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, low);
        val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
 
        WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);
index a9bc9d1..364162d 100644 (file)
@@ -243,14 +243,13 @@ static int vega20_thermal_set_temperature_range(struct pp_hwmgr *hwmgr,
        struct phm_ppt_v3_information *pptable_information =
                (struct phm_ppt_v3_information *)hwmgr->pptable;
        struct amdgpu_device *adev = hwmgr->adev;
-       int low = VEGA20_THERMAL_MINIMUM_ALERT_TEMP *
-                       PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
-       int high = VEGA20_THERMAL_MAXIMUM_ALERT_TEMP *
-                       PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
+       int low = VEGA20_THERMAL_MINIMUM_ALERT_TEMP;
+       int high = VEGA20_THERMAL_MAXIMUM_ALERT_TEMP;
        uint32_t val;
 
-       if (low < range->min)
-               low = range->min;
+       /* compare them in unit celsius degree */
+       if (low < range->min / PP_TEMPERATURE_UNITS_PER_CENTIGRADES)
+               low = range->min / PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
        if (high > pptable_information->us_software_shutdown_temp)
                high = pptable_information->us_software_shutdown_temp;
 
@@ -261,8 +260,8 @@ static int vega20_thermal_set_temperature_range(struct pp_hwmgr *hwmgr,
 
        val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
        val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
-       val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));
-       val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));
+       val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, high);
+       val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, low);
        val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
 
        WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);