projects
/
linux-2.6-microblaze.git
/ commitdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
| commitdiff |
tree
raw
|
patch
| inline |
side by side
(parent:
d55c571
)
x86/ibs: Fix typo in dc_l2tlb_miss comment
author
Xiang-Bin Shi
<eric91102091@gmail.com>
Fri, 23 Jan 2026 07:57:19 +0000
(15:57 +0800)
committer
Peter Zijlstra
<peterz@infradead.org>
Mon, 2 Feb 2026 21:01:07 +0000
(22:01 +0100)
The comment for dc_l2tlb_miss incorrectly describes it as a "hit".
This contradicts the field name and the actual bit definition.
Fix the comment to correctly describe it as a "miss".
Signed-off-by: Xiang-Bin Shi <eric91102091@gmail.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link:
https://patch.msgid.link/20260123075719.160734-1-eric91102091@gmail.com
arch/x86/include/asm/amd/ibs.h
patch
|
blob
|
history
diff --git
a/arch/x86/include/asm/amd/ibs.h
b/arch/x86/include/asm/amd/ibs.h
index
3ee5903
..
fcc8a5a
100644
(file)
--- a/
arch/x86/include/asm/amd/ibs.h
+++ b/
arch/x86/include/asm/amd/ibs.h
@@
-110,7
+110,7
@@
union ibs_op_data3 {
__u64 ld_op:1, /* 0: load op */
st_op:1, /* 1: store op */
dc_l1tlb_miss:1, /* 2: data cache L1TLB miss */
- dc_l2tlb_miss:1, /* 3: data cache L2TLB
hit
in 2M page */
+ dc_l2tlb_miss:1, /* 3: data cache L2TLB
miss
in 2M page */
dc_l1tlb_hit_2m:1, /* 4: data cache L1TLB hit in 2M page */
dc_l1tlb_hit_1g:1, /* 5: data cache L1TLB hit in 1G page */
dc_l2tlb_hit_2m:1, /* 6: data cache L2TLB hit in 2M page */