Merge tag 'mips_fixes_5.9_1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips...

Pull MIPS fixes from Thomas Bogendoerfer:
 "A few MIPS fixes:

   - fallthrough fallout fix

   - BMIPS fixes

   - MSA fix to avoid leaking MSA register contents

   - Loongson perf and cpu feature fix

   - SNI interrupt fix"

* tag 'mips_fixes_5.9_1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux:
  MIPS: SNI: Fix SCSI interrupt
  MIPS: add missing MSACSR and upper MSA initialization
  MIPS: perf: Fix wrong check condition of Loongson event IDs
  mips/oprofile: Fix fallthrough placement
  MIPS: Loongson64: Remove unnecessary inclusion of boot_param.h
  MIPS: BMIPS: Also call bmips_cpu_setup() for secondary cores
  MIPS: mm: BMIPS5000 has inclusive physical caches
  MIPS: Loongson64: Do not override watch and ejtag feature

diff --git a/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h b/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h
index b6e9c99..eb18122 100644 (file)
--- a/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h
@@ -26,7 +26,6 @@
 #define cpu_has_counter                1
 #define cpu_has_dc_aliases     (PAGE_SIZE < 0x4000)
 #define cpu_has_divec          0
-#define cpu_has_ejtag          0
 #define cpu_has_inclusive_pcaches      1
 #define cpu_has_llsc           1
 #define cpu_has_mcheck         0
@@ -42,7 +41,6 @@
 #define cpu_has_veic           0
 #define cpu_has_vint           0
 #define cpu_has_vtag_icache    0
-#define cpu_has_watch          1
 #define cpu_has_wsbh           1
 #define cpu_has_ic_fills_f_dc  1
 #define cpu_hwrena_impl_bits   0xc0000000

diff --git a/arch/mips/include/asm/mach-loongson64/irq.h b/arch/mips/include/asm/mach-loongson64/irq.h
index f5e362f..bf24809 100644 (file)
--- a/arch/mips/include/asm/mach-loongson64/irq.h
+++ b/arch/mips/include/asm/mach-loongson64/irq.h
@@ -2,8 +2,6 @@
 #ifndef __ASM_MACH_LOONGSON64_IRQ_H_
 #define __ASM_MACH_LOONGSON64_IRQ_H_
 
-#include <boot_param.h>
-
 /* cpu core interrupt numbers */
 #define NR_IRQS_LEGACY         16
 #define NR_MIPS_CPU_IRQS       8

diff --git a/arch/mips/include/asm/mach-loongson64/mmzone.h b/arch/mips/include/asm/mach-loongson64/mmzone.h
index 3a25dbd..5eaca4f 100644 (file)
--- a/arch/mips/include/asm/mach-loongson64/mmzone.h
+++ b/arch/mips/include/asm/mach-loongson64/mmzone.h
@@ -9,7 +9,6 @@
 #ifndef _ASM_MACH_LOONGSON64_MMZONE_H
 #define _ASM_MACH_LOONGSON64_MMZONE_H
 
-#include <boot_param.h>
 #define NODE_ADDRSPACE_SHIFT 44
 #define NODE0_ADDRSPACE_OFFSET 0x000000000000UL
 #define NODE1_ADDRSPACE_OFFSET 0x100000000000UL

diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c
index efce5de..011eb6b 100644 (file)
--- a/arch/mips/kernel/perf_event_mipsxx.c
+++ b/arch/mips/kernel/perf_event_mipsxx.c
@@ -1898,8 +1898,8 @@ static const struct mips_perf_event *mipsxx_pmu_map_raw_event(u64 config)
                                (base_id >= 64 && base_id < 90) ||
                                (base_id >= 128 && base_id < 164) ||
                                (base_id >= 192 && base_id < 200) ||
-                               (base_id >= 256 && base_id < 274) ||
-                               (base_id >= 320 && base_id < 358) ||
+                               (base_id >= 256 && base_id < 275) ||
+                               (base_id >= 320 && base_id < 361) ||
                                (base_id >= 384 && base_id < 574))
                                break;
 

diff --git a/arch/mips/kernel/smp-bmips.c b/arch/mips/kernel/smp-bmips.c
index 2f51350..1dbfb5a 100644 (file)
--- a/arch/mips/kernel/smp-bmips.c
+++ b/arch/mips/kernel/smp-bmips.c
@@ -239,6 +239,8 @@ static int bmips_boot_secondary(int cpu, struct task_struct *idle)
  */
 static void bmips_init_secondary(void)
 {
+       bmips_cpu_setup();
+
        switch (current_cpu_type()) {
        case CPU_BMIPS4350:
        case CPU_BMIPS4380:

diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 38aa07c..cf78859 100644 (file)
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -1287,6 +1287,18 @@ static int enable_restore_fp_context(int msa)
                err = own_fpu_inatomic(1);
                if (msa && !err) {
                        enable_msa();
+                       /*
+                        * with MSA enabled, userspace can see MSACSR
+                        * and MSA regs, but the values in them are from
+                        * other task before current task, restore them
+                        * from saved fp/msa context
+                        */
+                       write_msa_csr(current->thread.fpu.msacsr);
+                       /*
+                        * own_fpu_inatomic(1) just restore low 64bit,
+                        * fix the high 64bit
+                        */
+                       init_msa_upper();
                        set_thread_flag(TIF_USEDMSA);
                        set_thread_flag(TIF_MSA_CTX_LIVE);
                }

diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index fc5a6d2..0ef7170 100644 (file)
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1712,7 +1712,11 @@ static void setup_scache(void)
                                printk("MIPS secondary cache %ldkB, %s, linesize %d bytes.\n",
                                       scache_size >> 10,
                                       way_string[c->scache.ways], c->scache.linesz);
+
+                               if (current_cpu_type() == CPU_BMIPS5000)
+                                       c->options |= MIPS_CPU_INCLUSIVE_CACHES;
                        }
+
 #else
                        if (!(c->scache.flags & MIPS_CACHE_NOT_PRESENT))
                                panic("Dunno how to handle MIPS32 / MIPS64 second level cache");

diff --git a/arch/mips/oprofile/op_model_mipsxx.c b/arch/mips/oprofile/op_model_mipsxx.c
index 1493c49..55d7b7f 100644 (file)
--- a/arch/mips/oprofile/op_model_mipsxx.c
+++ b/arch/mips/oprofile/op_model_mipsxx.c
@@ -245,7 +245,6 @@ static int mipsxx_perfcount_handler(void)
 
        switch (counters) {
 #define HANDLE_COUNTER(n)                                              \
-       fallthrough;                                                    \
        case n + 1:                                                     \
                control = r_c0_perfctrl ## n();                         \
                counter = r_c0_perfcntr ## n();                         \
@@ -256,8 +255,11 @@ static int mipsxx_perfcount_handler(void)
                        handled = IRQ_HANDLED;                          \
                }
        HANDLE_COUNTER(3)
+       fallthrough;
        HANDLE_COUNTER(2)
+       fallthrough;
        HANDLE_COUNTER(1)
+       fallthrough;
        HANDLE_COUNTER(0)
        }
 

diff --git a/arch/mips/sni/a20r.c b/arch/mips/sni/a20r.c
index 0ecffb6..b09dc84 100644 (file)
--- a/arch/mips/sni/a20r.c
+++ b/arch/mips/sni/a20r.c
@@ -222,8 +222,8 @@ void __init sni_a20r_irq_init(void)
                irq_set_chip_and_handler(i, &a20r_irq_type, handle_level_irq);
        sni_hwint = a20r_hwint;
        change_c0_status(ST0_IM, IE_IRQ0);
-       if (request_irq(SNI_A20R_IRQ_BASE + 3, sni_isa_irq_handler, 0, "ISA",
-                       NULL))
+       if (request_irq(SNI_A20R_IRQ_BASE + 3, sni_isa_irq_handler,
+                       IRQF_SHARED, "ISA", sni_isa_irq_handler))
                pr_err("Failed to register ISA interrupt\n");
 }