PCI: designware-ep: Fix the Header Type check

The current check will result in the multiple function device
fails to initialize. So fix the check by masking out the
multiple function bit.

Link: https://lore.kernel.org/r/20200818092746.24366-1-Zhiqiang.Hou@nxp.com
Fixes: 0b24134f7888 ("PCI: dwc: Add validation that PCIe core is set to correct mode")
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Rob Herring <robh@kernel.org>

diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
index 305bfec..29f5c61 100644 (file)
--- a/drivers/pci/controller/dwc/pcie-designware-ep.c
+++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
@@ -505,7 +505,8 @@ int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep)
        u32 reg;
        int i;
 
-       hdr_type = dw_pcie_readb_dbi(pci, PCI_HEADER_TYPE);
+       hdr_type = dw_pcie_readb_dbi(pci, PCI_HEADER_TYPE) &
+                  PCI_HEADER_TYPE_MASK;
        if (hdr_type != PCI_HEADER_TYPE_NORMAL) {
                dev_err(pci->dev,
                        "PCIe controller is not set to EP mode (hdr_type:0x%x)!\n",

diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
index f970141..57a2220 100644 (file)
--- a/include/uapi/linux/pci_regs.h
+++ b/include/uapi/linux/pci_regs.h
@@ -76,6 +76,7 @@
 #define PCI_CACHE_LINE_SIZE    0x0c    /* 8 bits */
 #define PCI_LATENCY_TIMER      0x0d    /* 8 bits */
 #define PCI_HEADER_TYPE                0x0e    /* 8 bits */
+#define  PCI_HEADER_TYPE_MASK          0x7f
 #define  PCI_HEADER_TYPE_NORMAL                0
 #define  PCI_HEADER_TYPE_BRIDGE                1
 #define  PCI_HEADER_TYPE_CARDBUS       2