drm/i915: Fix audio power up sequence for gen10+ display

On platfroms with gen10+ display, driver must set the enable bit of
AUDIO_PIN_BUF_CTL register before transactions with the HDA controller
can proceed. Add setting this bit to the audio power up sequence.

Failing to do this resulted in errors during display audio codec probe,
and failures during resume from suspend.

Note: We may also need to disable the bit afterwards, but there are
still unresolved issues with that.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111214
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191003085531.30990-1-kai.vehmanen@linux.intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c
index 54638d9..e937767 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -862,6 +862,11 @@ static unsigned long i915_audio_component_get_power(struct device *kdev)
                /* Force CDCLK to 2*BCLK as long as we need audio powered. */
                if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
                        glk_force_audio_cdclk(dev_priv, true);
+
+               if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
+                       I915_WRITE(AUD_PIN_BUF_CTL,
+                                  (I915_READ(AUD_PIN_BUF_CTL) |
+                                   AUD_PIN_BUF_ENABLE));
        }
 
        return ret;

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index eefd789..813ddea 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9133,6 +9133,8 @@ enum {
 #define   SKL_AUD_CODEC_WAKE_SIGNAL            (1 << 15)
 
 #define AUD_FREQ_CNTRL                 _MMIO(0x65900)
+#define AUD_PIN_BUF_CTL                _MMIO(0x48414)
+#define   AUD_PIN_BUF_ENABLE           REG_BIT(31)
 
 /*
  * HSW - ICL power wells