drm/amd/display: Enable DTBCLK DTO earlier in the sequence

[why]
As per programming guide, we need to
enable the virtual pixel clock via DTBCLK
DTO and ungate the clock before we begin
programming OPP/OPTC control registers.
Otherwise, the double-buffered registers
will be left pending until the clocks are enabled.

[how]
Move the DTBCLK DTO programming up to
where we do the legacy DP DTO programming.

Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: Roman Li <roman.li@amd.com>
Signed-off-by: Sung Joon Kim <sungjoon.kim@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
index f983041..87b43cb 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
@@ -873,6 +873,22 @@ enum dc_status dcn20_enable_stream_timing(
                return DC_ERROR_UNEXPECTED;
        }
 
+       if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {
+               struct dccg *dccg = dc->res_pool->dccg;
+               struct timing_generator *tg = pipe_ctx->stream_res.tg;
+               struct dtbclk_dto_params dto_params = {0};
+
+               if (dccg->funcs->set_dtbclk_p_src)
+                       dccg->funcs->set_dtbclk_p_src(dccg, DTBCLK0, tg->inst);
+
+               dto_params.otg_inst = tg->inst;
+               dto_params.pixclk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10;
+               dto_params.num_odm_segments = get_odm_segment_count(pipe_ctx);
+               dto_params.timing = &pipe_ctx->stream->timing;
+               dto_params.ref_dtbclk_khz = dc->clk_mgr->funcs->get_dtb_ref_clk_frequency(dc->clk_mgr);
+               dccg->funcs->set_dtbclk_dto(dccg, &dto_params);
+       }
+
        if (dc_is_hdmi_tmds_signal(stream->signal)) {
                stream->link->phy_state.symclk_ref_cnts.otg = 1;
                if (stream->link->phy_state.symclk_state == SYMCLK_OFF_TX_OFF)
@@ -959,22 +975,6 @@ enum dc_status dcn20_enable_stream_timing(
                        pipe_ctx->stream_res.tg->funcs->phantom_crtc_post_enable(pipe_ctx->stream_res.tg);
        }
 
-       if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {
-               struct dccg *dccg = dc->res_pool->dccg;
-               struct timing_generator *tg = pipe_ctx->stream_res.tg;
-               struct dtbclk_dto_params dto_params = {0};
-
-               if (dccg->funcs->set_dtbclk_p_src)
-                       dccg->funcs->set_dtbclk_p_src(dccg, DTBCLK0, tg->inst);
-
-               dto_params.otg_inst = tg->inst;
-               dto_params.pixclk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10;
-               dto_params.num_odm_segments = get_odm_segment_count(pipe_ctx);
-               dto_params.timing = &pipe_ctx->stream->timing;
-               dto_params.ref_dtbclk_khz = dc->clk_mgr->funcs->get_dtb_ref_clk_frequency(dc->clk_mgr);
-               dccg->funcs->set_dtbclk_dto(dccg, &dto_params);
-       }
-
        return DC_OK;
 }