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drm/i915/gt: Set the PD again for Haswell
authorChris Wilson <chris@chris-wilson.co.uk>
Tue, 3 Dec 2019 21:16:31 +0000 (21:16 +0000)
committerChris Wilson <chris@chris-wilson.co.uk>
Tue, 3 Dec 2019 23:50:19 +0000 (23:50 +0000)
And Haswell still occasionally forgets it is meant to be using a new
page directory, so repeat ourselves a little louder.

<7> [509.919864] heartbeat rcs0 heartbeat {prio:-2147483645} not ticking
<7> [509.919895] heartbeat  Awake? 8
<7> [509.919903] heartbeat  Barriers?: no
<7> [509.919912] heartbeat  Heartbeat: 3008 ms ago
<7> [509.919930] heartbeat  Reset count: 0 (global 0)
<7> [509.919937] heartbeat  Requests:
<7> [509.921008] heartbeat  active  a7eb:56e1*  @ 5847ms:
<7> [509.921157] heartbeat  ring->start:  0x00001000
<7> [509.921164] heartbeat  ring->head:   0x00001610
<7> [509.921170] heartbeat  ring->tail:   0x000023d8
<7> [509.921176] heartbeat  ring->emit:   0x000023d8
<7> [509.921182] heartbeat  ring->space:  0x00002570
<7> [509.921189] heartbeat  ring->hwsp:   0x7fffe100
<7> [509.921197] heartbeat [head 1628, postfix 1738, tail 1750, batch 0xffffffff_ffffffff]:
<7> [509.921289] heartbeat [0000] 7a000002 00100002 00000000 00000000 7a000002 01154c1e 7ffff080 00000000
<7> [509.921299] heartbeat [0020] 11000001 00002220 ffffffff 12400001 00002220 7ffff000 00000000 11000001
<7> [509.921308] heartbeat [0040] 00002228 6e900000 7a000002 00100002 00000000 00000000 7a000002 01154c1e
<7> [509.921317] heartbeat [0060] 7ffff080 00000000 12400001 00002228 7ffff000 00000000 7a000002 00100002
<7> [509.921326] heartbeat [0080] 00000000 00000000 7a000002 01154c1e 7ffff080 00000000 7a000002 001010a1
<7> [509.921335] heartbeat [00a0] 7ffff080 00000000 04000000 11000005 00022050 00010001 00012050 00010001
<7> [509.921345] heartbeat [00c0] 0001a050 00010001 00000000 0c000000 459a110c 00000000 11000005 00022050
<7> [509.921354] heartbeat [00e0] 00010000 00012050 00010000 0001a050 00010000 12400001 0001a050 7ffff000
<7> [509.921363] heartbeat [0100] 00000000 04000001 18802100 00000000 7a000002 011050a1 7fffe100 000056e1
<7> [509.921370] heartbeat [0120] 01000000 00000000
<7> [509.921538] heartbeat  MMIO base:  0x00002000
<7> [509.921682] heartbeat  CCID: 0x3fa0110d
<7> [509.922342] heartbeat  RING_START: 0x00001000
<7> [509.922353] heartbeat  RING_HEAD:  0x00001628
<7> [509.922366] heartbeat  RING_TAIL:  0x000023d8
<7> [509.922381] heartbeat  RING_CTL:   0x00003001
<7> [509.922396] heartbeat  RING_MODE:  0x00004000
<7> [509.922408] heartbeat  RING_IMR: ffffffde
<7> [509.922421] heartbeat  ACTHD:  0x00000000_30e01628
<7> [509.922434] heartbeat  BBADDR: 0x00000000_00004004
<7> [509.922446] heartbeat  DMA_FADDR: 0x00000000_00002800
<7> [509.922458] heartbeat  IPEIR: 0x00000000
<7> [509.922470] heartbeat  IPEHR: 0x780c0000
<7> [509.922642] heartbeat  PP_DIR_BASE: 0x6e700000
<7> [509.922652] heartbeat  PP_DIR_BASE_READ: 0x00000000
<7> [509.922662] heartbeat  PP_DIR_DCLV: 0xffffffff
<7> [509.922678] heartbeat  E  a7eb:56e1*  @ 5849ms:
<7> [509.922689] heartbeat  E  a7eb:56e2-  @ 5849ms:
<7> [509.922698] heartbeat  E  a7eb:56e3  @ 5848ms:
<7> [509.922707] heartbeat  E  a7eb:56e4  @ 5848ms:
<7> [509.922715] heartbeat  E  a7eb:56e5  @ 5847ms:
<7> [509.922724] heartbeat  E  a7eb:56e6  @ 5846ms:
<7> [509.922735] heartbeat  E  a7eb:56e7  @ 5846ms:
<7> [509.922744] heartbeat  ...skipping 4 executing requests...
<7> [509.922754] heartbeat  E  a7eb:56ec  @ 3010ms:
<7> [509.922796] heartbeat HWSP:
<7> [509.922807] heartbeat [0000] 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000
<7> [509.922817] heartbeat [0020] 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
<7> [509.922826] heartbeat *
<7> [509.922836] heartbeat [0100] 000056e0 00000000 00000000 00000000 00000000 00000000 00000000 00000000
<7> [509.922845] heartbeat [0120] 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
<7> [509.922851] heartbeat *
<7> [509.922870] heartbeat Idle? no
<7> [509.922878] heartbeat Signals:
<7> [509.923000] heartbeat  [a7eb:56e2] @ 5850ms

Here, we have a failed context restore after the PD switch, but note
that the PP_DIR_BASE register does not match the LRI in the ring.

Bump it to 8^W 4 loops, and with that Baytrail starts passing the sanity
checks.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191203211631.3167430-1-chris@chris-wilson.co.uk
drivers/gpu/drm/i915/gt/intel_ring_submission.c patch | blob | history
drivers/gpu/drm/i915/i915_pci.c patch | blob | history

diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
index 093cec1..42e3405 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
@@ -1368,7 +1368,7 @@ static int load_pd_dir(struct i915_request *rq, const struct i915_ppgtt *ppgtt)
        const struct intel_engine_cs * const engine = rq->engine;
        u32 *cs;
 
-       cs = intel_ring_begin(rq, 10);
+       cs = intel_ring_begin(rq, 12);
        if (IS_ERR(cs))
                return PTR_ERR(cs);
 
@@ -1380,34 +1380,19 @@ static int load_pd_dir(struct i915_request *rq, const struct i915_ppgtt *ppgtt)
        *cs++ = i915_mmio_reg_offset(RING_PP_DIR_DCLV(engine->mmio_base));
        *cs++ = intel_gt_scratch_offset(rq->engine->gt,
                                        INTEL_GT_SCRATCH_FIELD_DEFAULT);
-       *cs++ = MI_NOOP;
 
        *cs++ = MI_LOAD_REGISTER_IMM(1);
        *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base));
        *cs++ = px_base(ppgtt->pd)->ggtt_offset << 10;
 
-       intel_ring_advance(rq, cs);
-
-       return 0;
-}
-
-static int flush_pd_dir(struct i915_request *rq)
-{
-       const struct intel_engine_cs * const engine = rq->engine;
-       u32 *cs;
-
-       cs = intel_ring_begin(rq, 4);
-       if (IS_ERR(cs))
-               return PTR_ERR(cs);
-
-       /* Stall until the page table load is complete */
+       /* Stall until the page table load is complete? */
        *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
        *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base));
        *cs++ = intel_gt_scratch_offset(rq->engine->gt,
                                        INTEL_GT_SCRATCH_FIELD_DEFAULT);
-       *cs++ = MI_NOOP;
 
        intel_ring_advance(rq, cs);
+
        return 0;
 }
 
@@ -1593,19 +1578,7 @@ static int switch_context(struct i915_request *rq)
        GEM_BUG_ON(HAS_EXECLISTS(rq->i915));
 
        if (vm) {
-               struct intel_engine_cs *engine = rq->engine;
-
-               ret = load_pd_dir(rq, i915_vm_to_ppgtt(vm));
-               if (ret)
-                       return ret;
-
-               ret = engine->emit_flush(rq, EMIT_INVALIDATE);
-               if (ret)
-                       return ret;
-
-               ret = flush_pd_dir(rq);
-               if (ret)
-                       return ret;
+               int loops = 4; /* 2 for Haswell? 4 for Baytrail! */
 
                /*
                 * Not only do we need a full barrier (post-sync write) after
@@ -1615,11 +1588,17 @@ static int switch_context(struct i915_request *rq)
                 * post-sync op, this extra pass appears vital before a
                 * mm switch!
                 */
-               ret = engine->emit_flush(rq, EMIT_INVALIDATE);
-               if (ret)
-                       return ret;
+               do {
+                       ret = rq->engine->emit_flush(rq, EMIT_FLUSH);
+                       if (ret)
+                               return ret;
+
+                       ret = load_pd_dir(rq, i915_vm_to_ppgtt(vm));
+                       if (ret)
+                               return ret;
+               } while (--loops);
 
-               ret = engine->emit_flush(rq, EMIT_FLUSH);
+               ret = rq->engine->emit_flush(rq, EMIT_INVALIDATE);
                if (ret)
                        return ret;
        }
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 583e0cd..bba6b50 100644 (file)
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -493,7 +493,7 @@ static const struct intel_device_info intel_valleyview_info = {
        .has_rps = true,
        .display.has_gmch = 1,
        .display.has_hotplug = 1,
-       .ppgtt_type = INTEL_PPGTT_ALIASING,
+       .ppgtt_type = INTEL_PPGTT_FULL,
        .ppgtt_size = 31,
        .has_snoop = true,
        .has_coherent_ggtt = false,
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