drm/amd/display: add debugfs disallow edp psr

[Why]
fix reading edp rx crc timeout failure. after
bootup, kernel setup psr with dpcd 0x170 = 5. this
notify rx psr enable and let rx fw start checking crc
for fw internal logic. rx fw may not update crc read
count within dpcd 0x246. read count is always 0. this
will lead tx crc reading timeout.

[How]
add debugfs to let test app to disbable rx crc
checking for rx internal logic. then test app can read
rx crc dpcd 0x246 successfully.
expected app sequence is as below:
1. disable eDP PHY and notify eDP rx with dpcd 0x600 = 2.
2. echo 0x1 /sys/kernel/debug/dri/0/eDP-X/disallow_edp_enter_psr
3. enable eDP PHY and notify eDP rx with dpcd 0x600 = 1 but
   without dpcd 0x170 = 5.
4. read crc from rx dpcd 0x270, 0x246, etc.
5. echo 0x0 /sys/kernel/debug/dri/0/eDP-X/disallow_edp_enter_psr.
   this will let eDP back to normal with psr setup dpcd 0x170 = 5.

Reviewed-by: Wayne Lin <wayne.lin@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index d3dbbf2..9bdd1f8 100644 (file)
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -8570,7 +8570,12 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
                                amdgpu_dm_link_setup_replay(acrtc_state->stream->link, aconn);
                        } else if (acrtc_state->stream->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED &&
                                        !acrtc_state->stream->link->psr_settings.psr_feature_enabled) {
-                               amdgpu_dm_link_setup_psr(acrtc_state->stream);
+
+                               struct amdgpu_dm_connector *aconn = (struct amdgpu_dm_connector *)
+                                       acrtc_state->stream->dm_stream_context;
+
+                               if (!aconn->disallow_edp_enter_psr)
+                                       amdgpu_dm_link_setup_psr(acrtc_state->stream);
                        }
                }
 
@@ -8599,6 +8604,7 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
                            !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) &&
 #endif
                            !acrtc_state->stream->link->psr_settings.psr_allow_active &&
+                           !aconn->disallow_edp_enter_psr &&
                            (timestamp_ns -
                            acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns) >
                            500000000)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
index 9c1871b..09519b7 100644 (file)
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
@@ -693,6 +693,7 @@ struct amdgpu_dm_connector {
        struct drm_display_mode freesync_vid_base;
 
        int psr_skip_count;
+       bool disallow_edp_enter_psr;
 
        /* Record progress status of mst*/
        uint8_t mst_status;

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
index c5078e6..e23a0a2 100644 (file)
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
@@ -142,7 +142,12 @@ static void amdgpu_dm_crtc_set_panel_sr_feature(
                        amdgpu_dm_psr_disable(vblank_work->stream);
        } else if (link->psr_settings.psr_feature_enabled &&
                allow_sr_entry && !is_sr_active && !is_crc_window_active) {
-               amdgpu_dm_psr_enable(vblank_work->stream);
+
+               struct amdgpu_dm_connector *aconn =
+                       (struct amdgpu_dm_connector *) vblank_work->stream->dm_stream_context;
+
+               if (!aconn->disallow_edp_enter_psr)
+                       amdgpu_dm_psr_enable(vblank_work->stream);
        }
 }
 

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
index 85fc618..eee4945 100644 (file)
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
@@ -2971,6 +2971,53 @@ static int allow_edp_hotplug_detection_set(void *data, u64 val)
        return 0;
 }
 
+/* check if kernel disallow eDP enter psr state
+ * cat /sys/kernel/debug/dri/0/eDP-X/disallow_edp_enter_psr
+ * 0: allow edp enter psr; 1: disallow
+ */
+static int disallow_edp_enter_psr_get(void *data, u64 *val)
+{
+       struct amdgpu_dm_connector *aconnector = data;
+
+       *val = (u64) aconnector->disallow_edp_enter_psr;
+       return 0;
+}
+
+/* set kernel disallow eDP enter psr state
+ * echo 0x0 /sys/kernel/debug/dri/0/eDP-X/disallow_edp_enter_psr
+ * 0: allow edp enter psr; 1: disallow
+ *
+ * usage: test app read crc from PSR eDP rx.
+ *
+ * during kernel boot up, kernel write dpcd 0x170 = 5.
+ * this notify eDP rx psr enable and let rx check crc.
+ * rx fw will start checking crc for rx internal logic.
+ * crc read count within dpcd 0x246 is not updated and
+ * value is 0. when eDP tx driver wants to read rx crc
+ * from dpcd 0x246, 0x270, read count 0 lead tx driver
+ * timeout.
+ *
+ * to avoid this, we add this debugfs to let test app to disbable
+ * rx crc checking for rx internal logic. then test app can read
+ * non-zero crc read count.
+ *
+ * expected app sequence is as below:
+ * 1. disable eDP PHY and notify eDP rx with dpcd 0x600 = 2.
+ * 2. echo 0x1 /sys/kernel/debug/dri/0/eDP-X/disallow_edp_enter_psr
+ * 3. enable eDP PHY and notify eDP rx with dpcd 0x600 = 1 but
+ *    without dpcd 0x170 = 5.
+ * 4. read crc from rx dpcd 0x270, 0x246, etc.
+ * 5. echo 0x0 /sys/kernel/debug/dri/0/eDP-X/disallow_edp_enter_psr.
+ *    this will let eDP back to normal with psr setup dpcd 0x170 = 5.
+ */
+static int disallow_edp_enter_psr_set(void *data, u64 val)
+{
+       struct amdgpu_dm_connector *aconnector = data;
+
+       aconnector->disallow_edp_enter_psr = val ? true : false;
+       return 0;
+}
+
 static int dmub_trace_mask_set(void *data, u64 val)
 {
        struct amdgpu_device *adev = data;
@@ -3092,6 +3139,10 @@ DEFINE_DEBUGFS_ATTRIBUTE(allow_edp_hotplug_detection_fops,
                        allow_edp_hotplug_detection_get,
                        allow_edp_hotplug_detection_set, "%llu\n");
 
+DEFINE_DEBUGFS_ATTRIBUTE(disallow_edp_enter_psr_fops,
+                       disallow_edp_enter_psr_get,
+                       disallow_edp_enter_psr_set, "%llu\n");
+
 DEFINE_SHOW_ATTRIBUTE(current_backlight);
 DEFINE_SHOW_ATTRIBUTE(target_backlight);
 
@@ -3265,6 +3316,8 @@ void connector_debugfs_init(struct amdgpu_dm_connector *connector)
                                        &edp_ilr_debugfs_fops);
                debugfs_create_file("allow_edp_hotplug_detection", 0644, dir, connector,
                                        &allow_edp_hotplug_detection_fops);
+               debugfs_create_file("disallow_edp_enter_psr", 0644, dir, connector,
+                                       &disallow_edp_enter_psr_fops);
        }
 
        for (i = 0; i < ARRAY_SIZE(connector_debugfs_entries); i++) {