Merge tag 'renesas-clk-for-v5.19-tag2' of git://git.kernel.org/pub/scm/linux/kernel...

Pull Renesas clk driver updates from Geert Uytterhoeven:

 - Add support for the R-Car V4H and RZ/V2M SoCs
 - Add the Universal Flash Storage clock on R-Car S4-8
 - Add I2C, SSIF-2 (sound), USB, CANFD, OSTM (timer), WDT, SPI Multi
   I/O Bus, RSPI, TSU (thermal), and ADC clocks and resets on RZ/G2UL
 - Add display clock support on RZ/G2L
 - Miscellaneous fixes and improvements

* tag 'renesas-clk-for-v5.19-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: (36 commits)
  clk: renesas: r9a09g011: Add eth clock and reset entries
  clk: renesas: Add RZ/V2M support using the rzg2l driver
  clk: renesas: rzg2l: Add support for RZ/V2M reset monitor reg
  clk: renesas: rzg2l: Make use of CLK_MON registers optional
  clk: renesas: rzg2l: Set HIWORD mask for all mux and dividers
  clk: renesas: rzg2l: Add read only versions of the clk macros
  clk: renesas: rzg2l: Move the DEF_MUX array size calc into the macro
  dt-bindings: clock: renesas,rzg2l: Document RZ/V2M SoC
  clk: renesas: r9a07g044: Fix OSTM1 module clock name
  clk: renesas: r9a07g043: Add clock and reset entries for ADC
  clk: renesas: r9a07g043: Add TSU clock and reset entry
  clk: renesas: r9a07g043: Add RSPI clock and reset entries
  clk: renesas: r9a07g043: Add clock and reset entries for SPI Multi I/O Bus Controller
  clk: renesas: r9a07g044: Add DSI clock and reset entries
  clk: renesas: r9a07g044: Add LCDC clock and reset entries
  clk: renesas: r9a07g044: Add M4 Clock support
  clk: renesas: r9a07g044: Add M3 Clock support
  clk: renesas: r9a07g044: Add {M2, M2_DIV2} Clocks support
  clk: renesas: r9a07g044: Add M1 clock support
  clk: renesas: rzg2l: Add DSI divider clk support
  ...