drm/amdgpu: Add nps_mode in RAS init_flag
authorCandice Li <candice.li@amd.com>
Thu, 17 Oct 2024 04:21:40 +0000 (12:21 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Mon, 4 Nov 2024 17:06:23 +0000 (12:06 -0500)
Add nps_mode in RAS init_flag.

Signed-off-by: Candice Li <candice.li@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
drivers/gpu/drm/amd/amdgpu/ta_ras_if.h

index ae24df6..17cf10c 100644 (file)
@@ -1834,6 +1834,9 @@ int psp_ras_initialize(struct psp_context *psp)
        ras_cmd->ras_in_message.init_flags.xcc_mask =
                adev->gfx.xcc_mask;
        ras_cmd->ras_in_message.init_flags.channel_dis_num = hweight32(adev->gmc.m_half_use) * 2;
+       if (adev->gmc.gmc_funcs->query_mem_partition_mode)
+               ras_cmd->ras_in_message.init_flags.nps_mode =
+                       adev->gmc.gmc_funcs->query_mem_partition_mode(adev);
 
        ret = psp_ta_load(psp, &psp->ras_context.context);
 
index 3ac56a9..21b71a4 100644 (file)
@@ -113,6 +113,14 @@ enum ta_ras_address_type {
        TA_RAS_PA_TO_MCA,
 };
 
+enum ta_ras_nps_mode {
+       TA_RAS_UNKNOWN_MODE = 0,
+       TA_RAS_NPS1_MODE = 1,
+       TA_RAS_NPS2_MODE = 2,
+       TA_RAS_NPS4_MODE = 4,
+       TA_RAS_NPS8_MODE = 8,
+};
+
 /* Input/output structures for RAS commands */
 /**********************************************************/
 
@@ -139,6 +147,7 @@ struct ta_ras_init_flags {
        uint8_t dgpu_mode;
        uint16_t xcc_mask;
        uint8_t channel_dis_num;
+       uint8_t nps_mode;
 };
 
 struct ta_ras_mca_addr {