For some Allwinner SoCs we have one pinctrl driver caring for multiple
very similar chips, and are tagging certain pins with a variant bitmask.
The Allwinner D1 introduced a slightly extended register layout, and we
were abusing this variant mask to convey this bit of information into
the common code part.
Now there will be more pinctrl device properties to consider (has PortF
voltage switch, for instance), so shoehorning this into the variant
bitmask will not fly anymore.
Refactor the "variant" field into a more generic "flags" field. It turns
out that we don't need the variant bits to be unique across all SoCs,
but only among those SoCs that share one driver (table), of which there
are at most three variants at the moment. So the actual variant field can
be limited to say 8 bits, and the other bits in the flag register can be
re-purposed to hold other information, like this extended register
layout.
As a side effect we can move the variant definition into the per-SoC
pinctrl driver file, which makes it more obvious that this is just a
private definition, only relevant for this particular table.
This also changes the artificial sun20i-d1 "variant" into the actual
flag bit that we are after.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/20250306235827.4895-2-andre.przywara@arm.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
static int d1_pinctrl_probe(struct platform_device *pdev)
{
- unsigned long variant = (unsigned long)of_device_get_match_data(&pdev->dev);
-
- return sunxi_pinctrl_init_with_variant(pdev, &d1_pinctrl_data, variant);
+ return sunxi_pinctrl_init_with_flags(pdev, &d1_pinctrl_data,
+ SUNXI_PINCTRL_NEW_REG_LAYOUT);
}
static const struct of_device_id d1_pinctrl_match[] = {
{
.compatible = "allwinner,sun20i-d1-pinctrl",
- .data = (void *)PINCTRL_SUN20I_D1
},
{}
};
#include "pinctrl-sunxi.h"
+#define PINCTRL_SUN4I_A10 BIT(0)
+#define PINCTRL_SUN7I_A20 BIT(1)
+#define PINCTRL_SUN8I_R40 BIT(2)
+
static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
{
unsigned long variant = (unsigned long)of_device_get_match_data(&pdev->dev);
- return sunxi_pinctrl_init_with_variant(pdev, &sun4i_a10_pinctrl_data,
- variant);
+ return sunxi_pinctrl_init_with_flags(pdev, &sun4i_a10_pinctrl_data,
+ variant);
}
static const struct of_device_id sun4i_a10_pinctrl_match[] = {
#include "pinctrl-sunxi.h"
+#define PINCTRL_SUN5I_A10S BIT(0)
+#define PINCTRL_SUN5I_A13 BIT(1)
+#define PINCTRL_SUN5I_GR8 BIT(2)
+
static const struct sunxi_desc_pin sun5i_pins[] = {
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(A, 0),
PINCTRL_SUN5I_A10S,
{
unsigned long variant = (unsigned long)of_device_get_match_data(&pdev->dev);
- return sunxi_pinctrl_init_with_variant(pdev, &sun5i_pinctrl_data,
- variant);
+ return sunxi_pinctrl_init_with_flags(pdev, &sun5i_pinctrl_data,
+ variant);
}
static const struct of_device_id sun5i_pinctrl_match[] = {
#include "pinctrl-sunxi.h"
+#define PINCTRL_SUN6I_A31 BIT(0)
+#define PINCTRL_SUN6I_A31S BIT(1)
+
static const struct sunxi_desc_pin sun6i_a31_pins[] = {
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
unsigned long variant =
(unsigned long)of_device_get_match_data(&pdev->dev);
- return sunxi_pinctrl_init_with_variant(pdev,
- &sun6i_a31_pinctrl_data,
- variant);
+ return sunxi_pinctrl_init_with_flags(pdev, &sun6i_a31_pinctrl_data,
+ variant);
}
static const struct of_device_id sun6i_a31_pinctrl_match[] = {
#include "pinctrl-sunxi.h"
+#define PINCTRL_SUN8I_V3 BIT(0)
+#define PINCTRL_SUN8I_V3S BIT(1)
+
static const struct sunxi_desc_pin sun8i_v3s_pins[] = {
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
{
unsigned long variant = (unsigned long)of_device_get_match_data(&pdev->dev);
- return sunxi_pinctrl_init_with_variant(pdev, &sun8i_v3s_pinctrl_data,
- variant);
+ return sunxi_pinctrl_init_with_flags(pdev, &sun8i_v3s_pinctrl_data,
+ variant);
}
static const struct of_device_id sun8i_v3s_pinctrl_match[] = {
return 0;
}
-int sunxi_pinctrl_init_with_variant(struct platform_device *pdev,
- const struct sunxi_pinctrl_desc *desc,
- unsigned long variant)
+int sunxi_pinctrl_init_with_flags(struct platform_device *pdev,
+ const struct sunxi_pinctrl_desc *desc,
+ unsigned long flags)
{
struct device_node *node = pdev->dev.of_node;
struct pinctrl_desc *pctrl_desc;
pctl->dev = &pdev->dev;
pctl->desc = desc;
- pctl->variant = variant;
- if (pctl->variant >= PINCTRL_SUN20I_D1) {
+ pctl->variant = flags & SUNXI_PINCTRL_VARIANT_MASK;
+ if (flags & SUNXI_PINCTRL_NEW_REG_LAYOUT) {
pctl->bank_mem_size = D1_BANK_MEM_SIZE;
pctl->pull_regs_offset = D1_PULL_REGS_OFFSET;
pctl->dlevel_field_width = D1_DLEVEL_FIELD_WIDTH;
#define SUN4I_FUNC_INPUT 0
#define SUN4I_FUNC_IRQ 6
-#define PINCTRL_SUN5I_A10S BIT(1)
-#define PINCTRL_SUN5I_A13 BIT(2)
-#define PINCTRL_SUN5I_GR8 BIT(3)
-#define PINCTRL_SUN6I_A31 BIT(4)
-#define PINCTRL_SUN6I_A31S BIT(5)
-#define PINCTRL_SUN4I_A10 BIT(6)
-#define PINCTRL_SUN7I_A20 BIT(7)
-#define PINCTRL_SUN8I_R40 BIT(8)
-#define PINCTRL_SUN8I_V3 BIT(9)
-#define PINCTRL_SUN8I_V3S BIT(10)
-/* Variants below here have an updated register layout. */
-#define PINCTRL_SUN20I_D1 BIT(11)
+#define SUNXI_PINCTRL_VARIANT_MASK GENMASK(7, 0)
+#define SUNXI_PINCTRL_NEW_REG_LAYOUT BIT(8)
+#define SUNXI_PINCTRL_PORTF_SWITCH BIT(9)
#define PIO_POW_MOD_SEL_REG 0x340
#define PIO_POW_MOD_CTL_REG 0x344
return GRP_CFG_REG + bank * 0x4;
}
-int sunxi_pinctrl_init_with_variant(struct platform_device *pdev,
- const struct sunxi_pinctrl_desc *desc,
- unsigned long variant);
+int sunxi_pinctrl_init_with_flags(struct platform_device *pdev,
+ const struct sunxi_pinctrl_desc *desc,
+ unsigned long flags);
#define sunxi_pinctrl_init(_dev, _desc) \
- sunxi_pinctrl_init_with_variant(_dev, _desc, 0)
+ sunxi_pinctrl_init_with_flags(_dev, _desc, 0)
#endif /* __PINCTRL_SUNXI_H */
projects / linux-2.6-microblaze.git / commitdiff