rtw88: 8821c: add cck pd settings
authorTzu-En Huang <tehuang@realtek.com>
Wed, 3 Jun 2020 09:42:14 +0000 (17:42 +0800)
committerKalle Valo <kvalo@codeaurora.org>
Wed, 15 Jul 2020 09:08:11 +0000 (12:08 +0300)
CCK PD can reduce the number of false alarm of the CCK rates.
It dynamically adjusts the power threshold and CS ratio.
The values are compared to the values of the previous level, if
the level is changed, set new values of power threshold and CS
ratio.

Implement rtw_chip_ops::cck_pd_set() for 8821c.

Signed-off-by: Tzu-En Huang <tehuang@realtek.com>
Signed-off-by: Yan-Hsuan Chuang <yhchuang@realtek.com>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
Link: https://lore.kernel.org/r/20200603094218.19942-2-yhchuang@realtek.com
drivers/net/wireless/realtek/rtw88/main.h
drivers/net/wireless/realtek/rtw88/rtw8821c.c
drivers/net/wireless/realtek/rtw88/rtw8821c.h

index 82b6acc..605a70e 100644 (file)
@@ -1483,6 +1483,7 @@ struct rtw_dm_info {
        /* [bandwidth 0:20M/1:40M][number of path] */
        u8 cck_pd_lv[2][RTW_RF_PATH_MAX];
        u32 cck_fa_avg;
+       u8 cck_pd_default;
 
        /* save the last rx phy status for debug */
        s8 rx_snr[RTW_RF_PATH_MAX];
index 4bd4164..904eb49 100644 (file)
@@ -102,6 +102,7 @@ static void rtw8821c_phy_set_param(struct rtw_dev *rtwdev)
        rtwdev->chip->ch_param[2] = rtw_read32_mask(rtwdev, REG_TXFILTER, MASKDWORD);
 
        rtw_phy_init(rtwdev);
+       rtwdev->dm_info.cck_pd_default = rtw_read8(rtwdev, REG_CSRATIO) & 0x1f;
 }
 
 static int rtw8821c_mac_init(struct rtw_dev *rtwdev)
@@ -596,6 +597,29 @@ static void rtw8821c_phy_calibration(struct rtw_dev *rtwdev)
        rtw8821c_do_iqk(rtwdev);
 }
 
+static void rtw8821c_phy_cck_pd_set(struct rtw_dev *rtwdev, u8 new_lvl)
+{
+       struct rtw_dm_info *dm_info = &rtwdev->dm_info;
+       u8 pd[CCK_PD_LV_MAX] = {3, 7, 13, 13, 13};
+
+       if (dm_info->min_rssi > 60) {
+               new_lvl = 4;
+               pd[4] = 0x1d;
+               goto set_cck_pd;
+       }
+
+       if (dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A] == new_lvl)
+               return;
+
+       dm_info->cck_fa_avg = CCK_FA_AVG_RESET;
+
+set_cck_pd:
+       dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A] = new_lvl;
+       rtw_write32_mask(rtwdev, REG_PWRTH, 0x3f0000, pd[new_lvl]);
+       rtw_write32_mask(rtwdev, REG_PWRTH2, 0x1f0000,
+                        dm_info->cck_pd_default + new_lvl * 2);
+}
+
 static struct rtw_pwr_seq_cmd trans_carddis_to_cardemu_8821c[] = {
        {0x0086,
         RTW_PWR_CUT_ALL_MSK,
@@ -1035,6 +1059,7 @@ static struct rtw_chip_ops rtw8821c_ops = {
        .cfg_ldo25              = rtw8821c_cfg_ldo25,
        .false_alarm_statistics = rtw8821c_false_alarm_statistics,
        .phy_calibration        = rtw8821c_phy_calibration,
+       .cck_pd_set             = rtw8821c_phy_cck_pd_set,
 };
 
 struct rtw_chip_info rtw8821c_hw_spec = {
index 3b7d12b..bc66b91 100644 (file)
@@ -186,11 +186,14 @@ _rtw_write32s_mask(struct rtw_dev *rtwdev, u32 addr, u32 mask, u32 data)
 #define REG_FAS                0x9a4
 #define REG_RXSB       0xa00
 #define REG_ADCINI     0xa04
+#define REG_PWRTH      0xa08
 #define REG_TXSF2      0xa24
 #define REG_TXSF6      0xa28
 #define REG_FA_CCK     0xa5c
 #define REG_RXDESC     0xa2c
 #define REG_ENTXCCK    0xa80
+#define REG_PWRTH2     0xaa8
+#define REG_CSRATIO    0xaaa
 #define REG_TXFILTER   0xaac
 #define REG_CNTRST     0xb58
 #define REG_AGCTR_A    0xc08