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mfd: sec-irq: Convert to using REGMAP_IRQ_REG() macros
authorAndré Draszik <andre.draszik@linaro.org>
Wed, 9 Apr 2025 20:37:43 +0000 (21:37 +0100)
committerLee Jones <lee@kernel.org>
Fri, 23 May 2025 07:48:49 +0000 (08:48 +0100)
Use REGMAP_IRQ_REG macro helpers instead of open coding. This makes the
code a bit shorter and more obvious.

Signed-off-by: André Draszik <andre.draszik@linaro.org>
Link: https://lore.kernel.org/r/20250409-s2mpg10-v4-22-d66d5f39b6bf@linaro.org
Signed-off-by: Lee Jones <lee@kernel.org>
drivers/mfd/sec-irq.c patch | blob | history

diff --git a/drivers/mfd/sec-irq.c b/drivers/mfd/sec-irq.c
index 4a6585a..c5c80b1 100644 (file)
--- a/drivers/mfd/sec-irq.c
+++ b/drivers/mfd/sec-irq.c
@@ -74,212 +74,68 @@ static const struct regmap_irq s2mpg10_irqs[] = {
 };
 
 static const struct regmap_irq s2mps11_irqs[] = {
-       [S2MPS11_IRQ_PWRONF] = {
-               .reg_offset = 0,
-               .mask = S2MPS11_IRQ_PWRONF_MASK,
-       },
-       [S2MPS11_IRQ_PWRONR] = {
-               .reg_offset = 0,
-               .mask = S2MPS11_IRQ_PWRONR_MASK,
-       },
-       [S2MPS11_IRQ_JIGONBF] = {
-               .reg_offset = 0,
-               .mask = S2MPS11_IRQ_JIGONBF_MASK,
-       },
-       [S2MPS11_IRQ_JIGONBR] = {
-               .reg_offset = 0,
-               .mask = S2MPS11_IRQ_JIGONBR_MASK,
-       },
-       [S2MPS11_IRQ_ACOKBF] = {
-               .reg_offset = 0,
-               .mask = S2MPS11_IRQ_ACOKBF_MASK,
-       },
-       [S2MPS11_IRQ_ACOKBR] = {
-               .reg_offset = 0,
-               .mask = S2MPS11_IRQ_ACOKBR_MASK,
-       },
-       [S2MPS11_IRQ_PWRON1S] = {
-               .reg_offset = 0,
-               .mask = S2MPS11_IRQ_PWRON1S_MASK,
-       },
-       [S2MPS11_IRQ_MRB] = {
-               .reg_offset = 0,
-               .mask = S2MPS11_IRQ_MRB_MASK,
-       },
-       [S2MPS11_IRQ_RTC60S] = {
-               .reg_offset = 1,
-               .mask = S2MPS11_IRQ_RTC60S_MASK,
-       },
-       [S2MPS11_IRQ_RTCA1] = {
-               .reg_offset = 1,
-               .mask = S2MPS11_IRQ_RTCA1_MASK,
-       },
-       [S2MPS11_IRQ_RTCA0] = {
-               .reg_offset = 1,
-               .mask = S2MPS11_IRQ_RTCA0_MASK,
-       },
-       [S2MPS11_IRQ_SMPL] = {
-               .reg_offset = 1,
-               .mask = S2MPS11_IRQ_SMPL_MASK,
-       },
-       [S2MPS11_IRQ_RTC1S] = {
-               .reg_offset = 1,
-               .mask = S2MPS11_IRQ_RTC1S_MASK,
-       },
-       [S2MPS11_IRQ_WTSR] = {
-               .reg_offset = 1,
-               .mask = S2MPS11_IRQ_WTSR_MASK,
-       },
-       [S2MPS11_IRQ_INT120C] = {
-               .reg_offset = 2,
-               .mask = S2MPS11_IRQ_INT120C_MASK,
-       },
-       [S2MPS11_IRQ_INT140C] = {
-               .reg_offset = 2,
-               .mask = S2MPS11_IRQ_INT140C_MASK,
-       },
+       REGMAP_IRQ_REG(S2MPS11_IRQ_PWRONF, 0, S2MPS11_IRQ_PWRONF_MASK),
+       REGMAP_IRQ_REG(S2MPS11_IRQ_PWRONR, 0, S2MPS11_IRQ_PWRONR_MASK),
+       REGMAP_IRQ_REG(S2MPS11_IRQ_JIGONBF, 0, S2MPS11_IRQ_JIGONBF_MASK),
+       REGMAP_IRQ_REG(S2MPS11_IRQ_JIGONBR, 0, S2MPS11_IRQ_JIGONBR_MASK),
+       REGMAP_IRQ_REG(S2MPS11_IRQ_ACOKBF, 0, S2MPS11_IRQ_ACOKBF_MASK),
+       REGMAP_IRQ_REG(S2MPS11_IRQ_ACOKBR, 0, S2MPS11_IRQ_ACOKBR_MASK),
+       REGMAP_IRQ_REG(S2MPS11_IRQ_PWRON1S, 0, S2MPS11_IRQ_PWRON1S_MASK),
+       REGMAP_IRQ_REG(S2MPS11_IRQ_MRB, 0, S2MPS11_IRQ_MRB_MASK),
+
+       REGMAP_IRQ_REG(S2MPS11_IRQ_RTC60S, 1, S2MPS11_IRQ_RTC60S_MASK),
+       REGMAP_IRQ_REG(S2MPS11_IRQ_RTCA1, 1, S2MPS11_IRQ_RTCA1_MASK),
+       REGMAP_IRQ_REG(S2MPS11_IRQ_RTCA0, 1, S2MPS11_IRQ_RTCA0_MASK),
+       REGMAP_IRQ_REG(S2MPS11_IRQ_SMPL, 1, S2MPS11_IRQ_SMPL_MASK),
+       REGMAP_IRQ_REG(S2MPS11_IRQ_RTC1S, 1, S2MPS11_IRQ_RTC1S_MASK),
+       REGMAP_IRQ_REG(S2MPS11_IRQ_WTSR, 1, S2MPS11_IRQ_WTSR_MASK),
+
+       REGMAP_IRQ_REG(S2MPS11_IRQ_INT120C, 2, S2MPS11_IRQ_INT120C_MASK),
+       REGMAP_IRQ_REG(S2MPS11_IRQ_INT140C, 2, S2MPS11_IRQ_INT140C_MASK),
 };
 
 static const struct regmap_irq s2mps14_irqs[] = {
-       [S2MPS14_IRQ_PWRONF] = {
-               .reg_offset = 0,
-               .mask = S2MPS11_IRQ_PWRONF_MASK,
-       },
-       [S2MPS14_IRQ_PWRONR] = {
-               .reg_offset = 0,
-               .mask = S2MPS11_IRQ_PWRONR_MASK,
-       },
-       [S2MPS14_IRQ_JIGONBF] = {
-               .reg_offset = 0,
-               .mask = S2MPS11_IRQ_JIGONBF_MASK,
-       },
-       [S2MPS14_IRQ_JIGONBR] = {
-               .reg_offset = 0,
-               .mask = S2MPS11_IRQ_JIGONBR_MASK,
-       },
-       [S2MPS14_IRQ_ACOKBF] = {
-               .reg_offset = 0,
-               .mask = S2MPS11_IRQ_ACOKBF_MASK,
-       },
-       [S2MPS14_IRQ_ACOKBR] = {
-               .reg_offset = 0,
-               .mask = S2MPS11_IRQ_ACOKBR_MASK,
-       },
-       [S2MPS14_IRQ_PWRON1S] = {
-               .reg_offset = 0,
-               .mask = S2MPS11_IRQ_PWRON1S_MASK,
-       },
-       [S2MPS14_IRQ_MRB] = {
-               .reg_offset = 0,
-               .mask = S2MPS11_IRQ_MRB_MASK,
-       },
-       [S2MPS14_IRQ_RTC60S] = {
-               .reg_offset = 1,
-               .mask = S2MPS11_IRQ_RTC60S_MASK,
-       },
-       [S2MPS14_IRQ_RTCA1] = {
-               .reg_offset = 1,
-               .mask = S2MPS11_IRQ_RTCA1_MASK,
-       },
-       [S2MPS14_IRQ_RTCA0] = {
-               .reg_offset = 1,
-               .mask = S2MPS11_IRQ_RTCA0_MASK,
-       },
-       [S2MPS14_IRQ_SMPL] = {
-               .reg_offset = 1,
-               .mask = S2MPS11_IRQ_SMPL_MASK,
-       },
-       [S2MPS14_IRQ_RTC1S] = {
-               .reg_offset = 1,
-               .mask = S2MPS11_IRQ_RTC1S_MASK,
-       },
-       [S2MPS14_IRQ_WTSR] = {
-               .reg_offset = 1,
-               .mask = S2MPS11_IRQ_WTSR_MASK,
-       },
-       [S2MPS14_IRQ_INT120C] = {
-               .reg_offset = 2,
-               .mask = S2MPS11_IRQ_INT120C_MASK,
-       },
-       [S2MPS14_IRQ_INT140C] = {
-               .reg_offset = 2,
-               .mask = S2MPS11_IRQ_INT140C_MASK,
-       },
-       [S2MPS14_IRQ_TSD] = {
-               .reg_offset = 2,
-               .mask = S2MPS14_IRQ_TSD_MASK,
-       },
+       REGMAP_IRQ_REG(S2MPS14_IRQ_PWRONF, 0, S2MPS11_IRQ_PWRONF_MASK),
+       REGMAP_IRQ_REG(S2MPS14_IRQ_PWRONR, 0, S2MPS11_IRQ_PWRONR_MASK),
+       REGMAP_IRQ_REG(S2MPS14_IRQ_JIGONBF, 0, S2MPS11_IRQ_JIGONBF_MASK),
+       REGMAP_IRQ_REG(S2MPS14_IRQ_JIGONBR, 0, S2MPS11_IRQ_JIGONBR_MASK),
+       REGMAP_IRQ_REG(S2MPS14_IRQ_ACOKBF, 0, S2MPS11_IRQ_ACOKBF_MASK),
+       REGMAP_IRQ_REG(S2MPS14_IRQ_ACOKBR, 0, S2MPS11_IRQ_ACOKBR_MASK),
+       REGMAP_IRQ_REG(S2MPS14_IRQ_PWRON1S, 0, S2MPS11_IRQ_PWRON1S_MASK),
+       REGMAP_IRQ_REG(S2MPS14_IRQ_MRB, 0, S2MPS11_IRQ_MRB_MASK),
+
+       REGMAP_IRQ_REG(S2MPS14_IRQ_RTC60S, 1, S2MPS11_IRQ_RTC60S_MASK),
+       REGMAP_IRQ_REG(S2MPS14_IRQ_RTCA1, 1, S2MPS11_IRQ_RTCA1_MASK),
+       REGMAP_IRQ_REG(S2MPS14_IRQ_RTCA0, 1, S2MPS11_IRQ_RTCA0_MASK),
+       REGMAP_IRQ_REG(S2MPS14_IRQ_SMPL, 1, S2MPS11_IRQ_SMPL_MASK),
+       REGMAP_IRQ_REG(S2MPS14_IRQ_RTC1S, 1, S2MPS11_IRQ_RTC1S_MASK),
+       REGMAP_IRQ_REG(S2MPS14_IRQ_WTSR, 1, S2MPS11_IRQ_WTSR_MASK),
+
+       REGMAP_IRQ_REG(S2MPS14_IRQ_INT120C, 2, S2MPS11_IRQ_INT120C_MASK),
+       REGMAP_IRQ_REG(S2MPS14_IRQ_INT140C, 2, S2MPS11_IRQ_INT140C_MASK),
+       REGMAP_IRQ_REG(S2MPS14_IRQ_TSD, 2, S2MPS14_IRQ_TSD_MASK),
 };
 
 static const struct regmap_irq s2mpu02_irqs[] = {
-       [S2MPU02_IRQ_PWRONF] = {
-               .reg_offset = 0,
-               .mask = S2MPS11_IRQ_PWRONF_MASK,
-       },
-       [S2MPU02_IRQ_PWRONR] = {
-               .reg_offset = 0,
-               .mask = S2MPS11_IRQ_PWRONR_MASK,
-       },
-       [S2MPU02_IRQ_JIGONBF] = {
-               .reg_offset = 0,
-               .mask = S2MPS11_IRQ_JIGONBF_MASK,
-       },
-       [S2MPU02_IRQ_JIGONBR] = {
-               .reg_offset = 0,
-               .mask = S2MPS11_IRQ_JIGONBR_MASK,
-       },
-       [S2MPU02_IRQ_ACOKBF] = {
-               .reg_offset = 0,
-               .mask = S2MPS11_IRQ_ACOKBF_MASK,
-       },
-       [S2MPU02_IRQ_ACOKBR] = {
-               .reg_offset = 0,
-               .mask = S2MPS11_IRQ_ACOKBR_MASK,
-       },
-       [S2MPU02_IRQ_PWRON1S] = {
-               .reg_offset = 0,
-               .mask = S2MPS11_IRQ_PWRON1S_MASK,
-       },
-       [S2MPU02_IRQ_MRB] = {
-               .reg_offset = 0,
-               .mask = S2MPS11_IRQ_MRB_MASK,
-       },
-       [S2MPU02_IRQ_RTC60S] = {
-               .reg_offset = 1,
-               .mask = S2MPS11_IRQ_RTC60S_MASK,
-       },
-       [S2MPU02_IRQ_RTCA1] = {
-               .reg_offset = 1,
-               .mask = S2MPS11_IRQ_RTCA1_MASK,
-       },
-       [S2MPU02_IRQ_RTCA0] = {
-               .reg_offset = 1,
-               .mask = S2MPS11_IRQ_RTCA0_MASK,
-       },
-       [S2MPU02_IRQ_SMPL] = {
-               .reg_offset = 1,
-               .mask = S2MPS11_IRQ_SMPL_MASK,
-       },
-       [S2MPU02_IRQ_RTC1S] = {
-               .reg_offset = 1,
-               .mask = S2MPS11_IRQ_RTC1S_MASK,
-       },
-       [S2MPU02_IRQ_WTSR] = {
-               .reg_offset = 1,
-               .mask = S2MPS11_IRQ_WTSR_MASK,
-       },
-       [S2MPU02_IRQ_INT120C] = {
-               .reg_offset = 2,
-               .mask = S2MPS11_IRQ_INT120C_MASK,
-       },
-       [S2MPU02_IRQ_INT140C] = {
-               .reg_offset = 2,
-               .mask = S2MPS11_IRQ_INT140C_MASK,
-       },
-       [S2MPU02_IRQ_TSD] = {
-               .reg_offset = 2,
-               .mask = S2MPS14_IRQ_TSD_MASK,
-       },
+       REGMAP_IRQ_REG(S2MPU02_IRQ_PWRONF, 0, S2MPS11_IRQ_PWRONF_MASK),
+       REGMAP_IRQ_REG(S2MPU02_IRQ_PWRONR, 0, S2MPS11_IRQ_PWRONR_MASK),
+       REGMAP_IRQ_REG(S2MPU02_IRQ_JIGONBF, 0, S2MPS11_IRQ_JIGONBF_MASK),
+       REGMAP_IRQ_REG(S2MPU02_IRQ_JIGONBR, 0, S2MPS11_IRQ_JIGONBR_MASK),
+       REGMAP_IRQ_REG(S2MPU02_IRQ_ACOKBF, 0, S2MPS11_IRQ_ACOKBF_MASK),
+       REGMAP_IRQ_REG(S2MPU02_IRQ_ACOKBR, 0, S2MPS11_IRQ_ACOKBR_MASK),
+       REGMAP_IRQ_REG(S2MPU02_IRQ_PWRON1S, 0, S2MPS11_IRQ_PWRON1S_MASK),
+       REGMAP_IRQ_REG(S2MPU02_IRQ_MRB, 0, S2MPS11_IRQ_MRB_MASK),
+
+       REGMAP_IRQ_REG(S2MPU02_IRQ_RTC60S, 1, S2MPS11_IRQ_RTC60S_MASK),
+       REGMAP_IRQ_REG(S2MPU02_IRQ_RTCA1, 1, S2MPS11_IRQ_RTCA1_MASK),
+       REGMAP_IRQ_REG(S2MPU02_IRQ_RTCA0, 1, S2MPS11_IRQ_RTCA0_MASK),
+       REGMAP_IRQ_REG(S2MPU02_IRQ_SMPL, 1, S2MPS11_IRQ_SMPL_MASK),
+       REGMAP_IRQ_REG(S2MPU02_IRQ_RTC1S, 1, S2MPS11_IRQ_RTC1S_MASK),
+       REGMAP_IRQ_REG(S2MPU02_IRQ_WTSR, 1, S2MPS11_IRQ_WTSR_MASK),
+
+       REGMAP_IRQ_REG(S2MPU02_IRQ_INT120C, 2, S2MPS11_IRQ_INT120C_MASK),
+       REGMAP_IRQ_REG(S2MPU02_IRQ_INT140C, 2, S2MPS11_IRQ_INT140C_MASK),
+       REGMAP_IRQ_REG(S2MPU02_IRQ_TSD, 2, S2MPS14_IRQ_TSD_MASK),
 };
 
 static const struct regmap_irq s2mpu05_irqs[] = {
@@ -303,74 +159,25 @@ static const struct regmap_irq s2mpu05_irqs[] = {
 };
 
 static const struct regmap_irq s5m8767_irqs[] = {
-       [S5M8767_IRQ_PWRR] = {
-               .reg_offset = 0,
-               .mask = S5M8767_IRQ_PWRR_MASK,
-       },
-       [S5M8767_IRQ_PWRF] = {
-               .reg_offset = 0,
-               .mask = S5M8767_IRQ_PWRF_MASK,
-       },
-       [S5M8767_IRQ_PWR1S] = {
-               .reg_offset = 0,
-               .mask = S5M8767_IRQ_PWR1S_MASK,
-       },
-       [S5M8767_IRQ_JIGR] = {
-               .reg_offset = 0,
-               .mask = S5M8767_IRQ_JIGR_MASK,
-       },
-       [S5M8767_IRQ_JIGF] = {
-               .reg_offset = 0,
-               .mask = S5M8767_IRQ_JIGF_MASK,
-       },
-       [S5M8767_IRQ_LOWBAT2] = {
-               .reg_offset = 0,
-               .mask = S5M8767_IRQ_LOWBAT2_MASK,
-       },
-       [S5M8767_IRQ_LOWBAT1] = {
-               .reg_offset = 0,
-               .mask = S5M8767_IRQ_LOWBAT1_MASK,
-       },
-       [S5M8767_IRQ_MRB] = {
-               .reg_offset = 1,
-               .mask = S5M8767_IRQ_MRB_MASK,
-       },
-       [S5M8767_IRQ_DVSOK2] = {
-               .reg_offset = 1,
-               .mask = S5M8767_IRQ_DVSOK2_MASK,
-       },
-       [S5M8767_IRQ_DVSOK3] = {
-               .reg_offset = 1,
-               .mask = S5M8767_IRQ_DVSOK3_MASK,
-       },
-       [S5M8767_IRQ_DVSOK4] = {
-               .reg_offset = 1,
-               .mask = S5M8767_IRQ_DVSOK4_MASK,
-       },
-       [S5M8767_IRQ_RTC60S] = {
-               .reg_offset = 2,
-               .mask = S5M8767_IRQ_RTC60S_MASK,
-       },
-       [S5M8767_IRQ_RTCA1] = {
-               .reg_offset = 2,
-               .mask = S5M8767_IRQ_RTCA1_MASK,
-       },
-       [S5M8767_IRQ_RTCA2] = {
-               .reg_offset = 2,
-               .mask = S5M8767_IRQ_RTCA2_MASK,
-       },
-       [S5M8767_IRQ_SMPL] = {
-               .reg_offset = 2,
-               .mask = S5M8767_IRQ_SMPL_MASK,
-       },
-       [S5M8767_IRQ_RTC1S] = {
-               .reg_offset = 2,
-               .mask = S5M8767_IRQ_RTC1S_MASK,
-       },
-       [S5M8767_IRQ_WTSR] = {
-               .reg_offset = 2,
-               .mask = S5M8767_IRQ_WTSR_MASK,
-       },
+       REGMAP_IRQ_REG(S5M8767_IRQ_PWRR, 0, S5M8767_IRQ_PWRR_MASK),
+       REGMAP_IRQ_REG(S5M8767_IRQ_PWRF, 0, S5M8767_IRQ_PWRF_MASK),
+       REGMAP_IRQ_REG(S5M8767_IRQ_PWR1S, 0, S5M8767_IRQ_PWR1S_MASK),
+       REGMAP_IRQ_REG(S5M8767_IRQ_JIGR, 0, S5M8767_IRQ_JIGR_MASK),
+       REGMAP_IRQ_REG(S5M8767_IRQ_JIGF, 0, S5M8767_IRQ_JIGF_MASK),
+       REGMAP_IRQ_REG(S5M8767_IRQ_LOWBAT2, 0, S5M8767_IRQ_LOWBAT2_MASK),
+       REGMAP_IRQ_REG(S5M8767_IRQ_LOWBAT1, 0, S5M8767_IRQ_LOWBAT1_MASK),
+
+       REGMAP_IRQ_REG(S5M8767_IRQ_MRB, 1, S5M8767_IRQ_MRB_MASK),
+       REGMAP_IRQ_REG(S5M8767_IRQ_DVSOK2, 1, S5M8767_IRQ_DVSOK2_MASK),
+       REGMAP_IRQ_REG(S5M8767_IRQ_DVSOK3, 1, S5M8767_IRQ_DVSOK3_MASK),
+       REGMAP_IRQ_REG(S5M8767_IRQ_DVSOK4, 1, S5M8767_IRQ_DVSOK4_MASK),
+
+       REGMAP_IRQ_REG(S5M8767_IRQ_RTC60S, 2, S5M8767_IRQ_RTC60S_MASK),
+       REGMAP_IRQ_REG(S5M8767_IRQ_RTCA1, 2, S5M8767_IRQ_RTCA1_MASK),
+       REGMAP_IRQ_REG(S5M8767_IRQ_RTCA2, 2, S5M8767_IRQ_RTCA2_MASK),
+       REGMAP_IRQ_REG(S5M8767_IRQ_SMPL, 2, S5M8767_IRQ_SMPL_MASK),
+       REGMAP_IRQ_REG(S5M8767_IRQ_RTC1S, 2, S5M8767_IRQ_RTC1S_MASK),
+       REGMAP_IRQ_REG(S5M8767_IRQ_WTSR, 2, S5M8767_IRQ_WTSR_MASK),
 };
 
 /* All S2MPG10 interrupt sources are read-only and don't require clearing */
MicroBlaze GIT Repository