drm/i915/display/cnl+: Handle fused off DSC
authorJosé Roberto de Souza <jose.souza@intel.com>
Sat, 26 Oct 2019 00:13:23 +0000 (17:13 -0700)
committerJosé Roberto de Souza <jose.souza@intel.com>
Tue, 29 Oct 2019 19:12:49 +0000 (12:12 -0700)
DSC could be fused off, so not all GEN10+ platforms will support it.

Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Martin Peres <martin.peres@linux.intel.com>
Reviewed-by: Ramalingam C <ramalingam.c@intel.com>
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191026001323.216052-5-jose.souza@intel.com
drivers/gpu/drm/i915/display/intel_dp.c
drivers/gpu/drm/i915/i915_pci.c
drivers/gpu/drm/i915/i915_reg.h
drivers/gpu/drm/i915/intel_device_info.c
drivers/gpu/drm/i915/intel_device_info.h

index 521ce23..c24c6d3 100644 (file)
@@ -1888,6 +1888,9 @@ static bool intel_dp_source_supports_dsc(struct intel_dp *intel_dp,
 {
        struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 
+       if (!INTEL_INFO(dev_priv)->display.has_dsc)
+               return false;
+
        /* On TGL, DSC is supported on all Pipes */
        if (INTEL_GEN(dev_priv) >= 12)
                return true;
index 430da2d..1bb701d 100644 (file)
@@ -737,6 +737,7 @@ static const struct intel_device_info intel_coffeelake_gt3_info = {
        GEN9_FEATURES, \
        GEN(10), \
        .ddb_size = 1024, \
+       .display.has_dsc = 1, \
        .has_coherent_ggtt = false, \
        GLK_COLORS
 
index 32a5371..5894e46 100644 (file)
@@ -7755,6 +7755,7 @@ enum {
 #define   SKL_DFSM_PIPE_B_DISABLE      (1 << 21)
 #define   SKL_DFSM_PIPE_C_DISABLE      (1 << 28)
 #define   TGL_DFSM_PIPE_D_DISABLE      (1 << 22)
+#define   CNL_DFSM_DISPLAY_DSC_DISABLE (1 << 7)
 
 #define SKL_DSSM                               _MMIO(0x51004)
 #define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz                (1 << 31)
index fa64648..a5b5713 100644 (file)
@@ -990,6 +990,10 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
 
                if (INTEL_GEN(dev_priv) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE))
                        info->display.has_csr = 0;
+
+               if (INTEL_GEN(dev_priv) >= 10 &&
+                   (dfsm & CNL_DFSM_DISPLAY_DSC_DISABLE))
+                       info->display.has_dsc = 0;
        }
 
        /* Initialize slice/subslice/EU info */
index 64e4f19..4bdf8a6 100644 (file)
@@ -137,6 +137,7 @@ enum intel_ppgtt_type {
        func(has_ddi); \
        func(has_dp_mst); \
        func(has_dsb); \
+       func(has_dsc); \
        func(has_fbc); \
        func(has_gmch); \
        func(has_hdcp); \