drm/i915/hwmon: expose package temperature

Add hwmon support for temp1_input attribute, which will expose package
temperature in millidegree Celsius. With this in place we can monitor
package temperature using lm-sensors tool.

$ sensors
i915-pci-0300
Adapter: PCI adapter
in0:         990.00 mV
fan1:        1260 RPM
temp1:        +45.0°C
power1:           N/A  (max =  35.00 W)
energy1:      12.62 kJ

v2: Use switch case (Anshuman)
v3: Comment adjustment (Riana)

Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11276
Signed-off-by: Raag Jadav <raag.jadav@intel.com>
Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com>
Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
Reviewed-by: Riana Tauro <riana.tauro@intel.com>
Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240910105242.3357276-1-raag.jadav@intel.com

diff --git a/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon b/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon
index be4141a..a885e53 100644 (file)
--- a/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon
+++ b/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon
@@ -83,3 +83,11 @@ Contact:     intel-gfx@lists.freedesktop.org
 Description:   RO. Fan speed of device in RPM.
 
                Only supported for particular Intel i915 graphics platforms.
+
+What:          /sys/bus/pci/drivers/i915/.../hwmon/hwmon<i>/temp1_input
+Date:          November 2024
+KernelVersion: 6.12
+Contact:       intel-gfx@lists.freedesktop.org
+Description:   RO. GPU package temperature in millidegree Celsius.
+
+               Only supported for particular Intel i915 graphics platforms.

diff --git a/drivers/gpu/drm/i915/i915_hwmon.c b/drivers/gpu/drm/i915/i915_hwmon.c
index 17d30f6..7dfe178 100644 (file)
--- a/drivers/gpu/drm/i915/i915_hwmon.c
+++ b/drivers/gpu/drm/i915/i915_hwmon.c
@@ -7,6 +7,7 @@
 #include <linux/hwmon-sysfs.h>
 #include <linux/jiffies.h>
 #include <linux/types.h>
+#include <linux/units.h>
 
 #include "i915_drv.h"
 #include "i915_hwmon.h"
@@ -32,6 +33,7 @@
 
 struct hwm_reg {
        i915_reg_t gt_perf_status;
+       i915_reg_t pkg_temp;
        i915_reg_t pkg_power_sku_unit;
        i915_reg_t pkg_power_sku;
        i915_reg_t pkg_rapl_limit;
@@ -280,6 +282,7 @@ static const struct attribute_group *hwm_groups[] = {
 };
 
 static const struct hwmon_channel_info * const hwm_info[] = {
+       HWMON_CHANNEL_INFO(temp, HWMON_T_INPUT),
        HWMON_CHANNEL_INFO(in, HWMON_I_INPUT),
        HWMON_CHANNEL_INFO(power, HWMON_P_MAX | HWMON_P_RATED_MAX | HWMON_P_CRIT),
        HWMON_CHANNEL_INFO(energy, HWMON_E_INPUT),
@@ -310,6 +313,37 @@ static int hwm_pcode_write_i1(struct drm_i915_private *i915, u32 uval)
                                  POWER_SETUP_SUBCOMMAND_WRITE_I1, 0, uval);
 }
 
+static umode_t
+hwm_temp_is_visible(const struct hwm_drvdata *ddat, u32 attr)
+{
+       struct i915_hwmon *hwmon = ddat->hwmon;
+
+       if (attr == hwmon_temp_input && i915_mmio_reg_valid(hwmon->rg.pkg_temp))
+               return 0444;
+
+       return 0;
+}
+
+static int
+hwm_temp_read(struct hwm_drvdata *ddat, u32 attr, long *val)
+{
+       struct i915_hwmon *hwmon = ddat->hwmon;
+       intel_wakeref_t wakeref;
+       u32 reg_val;
+
+       switch (attr) {
+       case hwmon_temp_input:
+               with_intel_runtime_pm(ddat->uncore->rpm, wakeref)
+                       reg_val = intel_uncore_read(ddat->uncore, hwmon->rg.pkg_temp);
+
+               /* HW register value is in degrees Celsius, convert to millidegrees. */
+               *val = REG_FIELD_GET(TEMP_MASK, reg_val) * MILLIDEGREE_PER_DEGREE;
+               return 0;
+       default:
+               return -EOPNOTSUPP;
+       }
+}
+
 static umode_t
 hwm_in_is_visible(const struct hwm_drvdata *ddat, u32 attr)
 {
@@ -692,6 +726,8 @@ hwm_is_visible(const void *drvdata, enum hwmon_sensor_types type,
        struct hwm_drvdata *ddat = (struct hwm_drvdata *)drvdata;
 
        switch (type) {
+       case hwmon_temp:
+               return hwm_temp_is_visible(ddat, attr);
        case hwmon_in:
                return hwm_in_is_visible(ddat, attr);
        case hwmon_power:
@@ -714,6 +750,8 @@ hwm_read(struct device *dev, enum hwmon_sensor_types type, u32 attr,
        struct hwm_drvdata *ddat = dev_get_drvdata(dev);
 
        switch (type) {
+       case hwmon_temp:
+               return hwm_temp_read(ddat, attr, val);
        case hwmon_in:
                return hwm_in_read(ddat, attr, val);
        case hwmon_power:
@@ -810,6 +848,7 @@ hwm_get_preregistration_info(struct drm_i915_private *i915)
        hwmon->rg.gt_perf_status = GEN12_RPSTAT1;
 
        if (IS_DG1(i915) || IS_DG2(i915)) {
+               hwmon->rg.pkg_temp = PCU_PACKAGE_TEMPERATURE;
                hwmon->rg.pkg_power_sku_unit = PCU_PACKAGE_POWER_SKU_UNIT;
                hwmon->rg.pkg_power_sku = PCU_PACKAGE_POWER_SKU;
                hwmon->rg.pkg_rapl_limit = PCU_PACKAGE_RAPL_LIMIT;
@@ -817,6 +856,7 @@ hwm_get_preregistration_info(struct drm_i915_private *i915)
                hwmon->rg.energy_status_tile = INVALID_MMIO_REG;
                hwmon->rg.fan_speed = PCU_PWM_FAN_SPEED;
        } else {
+               hwmon->rg.pkg_temp = INVALID_MMIO_REG;
                hwmon->rg.pkg_power_sku_unit = INVALID_MMIO_REG;
                hwmon->rg.pkg_power_sku = INVALID_MMIO_REG;
                hwmon->rg.pkg_rapl_limit = INVALID_MMIO_REG;

diff --git a/drivers/gpu/drm/i915/intel_mchbar_regs.h b/drivers/gpu/drm/i915/intel_mchbar_regs.h
index 73900c0..dc24771 100644 (file)
--- a/drivers/gpu/drm/i915/intel_mchbar_regs.h
+++ b/drivers/gpu/drm/i915/intel_mchbar_regs.h
@@ -207,6 +207,10 @@
 #define PCU_PACKAGE_ENERGY_STATUS              _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x593c)
 
 #define GEN6_GT_PERF_STATUS                    _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5948)
+
+#define PCU_PACKAGE_TEMPERATURE                        _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5978)
+#define   TEMP_MASK                            REG_GENMASK(7, 0)
+
 #define GEN6_RP_STATE_LIMITS                   _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5994)
 #define GEN6_RP_STATE_CAP                      _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5998)
 #define   RP0_CAP_MASK                         REG_GENMASK(7, 0)