drm/i915/gt: Make WARN* drm specific where drm_priv ptr is available

drm specific WARN* calls include device information in the
backtrace, so we know what device the warnings originate from.

Covert all the calls of WARN* with device specific drm_WARN*
variants in functions where drm_i915_private struct pointer is readily
available.

The conversion was done automatically with below coccinelle semantic
patch. checkpatch errors/warnings are fixed manually.

@rule1@
identifier func, T;
@@
func(...) {
...
struct drm_i915_private *T = ...;
<+...
(
-WARN(
+drm_WARN(&T->drm,
...)
|
-WARN_ON(
+drm_WARN_ON(&T->drm,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(&T->drm,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(&T->drm,
...)
)
...+>
}

@rule2@
identifier func, T;
@@
func(struct drm_i915_private *T,...) {
<+...
(
-WARN(
+drm_WARN(&T->drm,
...)
|
-WARN_ON(
+drm_WARN_ON(&T->drm,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(&T->drm,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(&T->drm,
...)
)
...+>
}

command: spatch --sp-file <script> --dir drivers/gpu/drm/i915/gt \
					--linux-spacing --in-place

Signed-off-by: Pankaj Bharadiya <pankaj.laxminarayan.bharadiya@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200115034455.17658-7-pankaj.laxminarayan.bharadiya@intel.com

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index b4b69a3..084abc5 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -448,9 +448,9 @@ int intel_engines_init_mmio(struct intel_gt *gt)
        unsigned int i;
        int err;
 
-       WARN_ON(engine_mask == 0);
-       WARN_ON(engine_mask &
-               GENMASK(BITS_PER_TYPE(mask) - 1, I915_NUM_ENGINES));
+       drm_WARN_ON(&i915->drm, engine_mask == 0);
+       drm_WARN_ON(&i915->drm, engine_mask &
+                   GENMASK(BITS_PER_TYPE(mask) - 1, I915_NUM_ENGINES));
 
        if (i915_inject_probe_failure(i915))
                return -ENODEV;
@@ -471,7 +471,7 @@ int intel_engines_init_mmio(struct intel_gt *gt)
         * are added to the driver by a warning and disabling the forgotten
         * engines.
         */
-       if (WARN_ON(mask != engine_mask))
+       if (drm_WARN_ON(&i915->drm, mask != engine_mask))
                device_info->engine_mask = mask;
 
        RUNTIME_INFO(i915)->num_engines = hweight32(mask);

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c
index 9e7f12b..848dece 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_engine_user.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c
@@ -278,7 +278,8 @@ void intel_engines_driver_register(struct drm_i915_private *i915)
                        }
                }
 
-               if (WARN(errors, "Invalid UABI engine mapping found"))
+               if (drm_WARN(&i915->drm, errors,
+                            "Invalid UABI engine mapping found"))
                        i915->uabi_engines = RB_ROOT;
        }
 

diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c
index 16acdc5..45d8e00 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_gtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
@@ -448,9 +448,9 @@ void gtt_write_workarounds(struct intel_gt *gt)
                intel_uncore_write(uncore,
                                   HSW_GTT_CACHE_EN,
                                   can_use_gtt_cache ? GTT_CACHE_EN_ALL : 0);
-               WARN_ON_ONCE(can_use_gtt_cache &&
-                            intel_uncore_read(uncore,
-                                              HSW_GTT_CACHE_EN) == 0);
+               drm_WARN_ON_ONCE(&i915->drm, can_use_gtt_cache &&
+                                intel_uncore_read(uncore,
+                                                  HSW_GTT_CACHE_EN) == 0);
        }
 }
 

diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
index eeef90b..0afc1eb 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -300,8 +300,8 @@ static bool get_mocs_settings(const struct drm_i915_private *i915,
                table->n_entries = GEN9_NUM_MOCS_ENTRIES;
                table->table = broxton_mocs_table;
        } else {
-               WARN_ONCE(INTEL_GEN(i915) >= 9,
-                         "Platform that should have a MOCS table does not.\n");
+               drm_WARN_ONCE(&i915->drm, INTEL_GEN(i915) >= 9,
+                             "Platform that should have a MOCS table does not.\n");
                return false;
        }
 

diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c
index 04eeb77..01a99fd 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_rc6.c
+++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
@@ -715,7 +715,7 @@ u64 intel_rc6_residency_ns(struct intel_rc6 *rc6, const i915_reg_t reg)
         */
        i = (i915_mmio_reg_offset(reg) -
             i915_mmio_reg_offset(GEN6_GT_GFX_RC6_LOCKED)) / sizeof(u32);
-       if (WARN_ON_ONCE(i >= ARRAY_SIZE(rc6->cur_residency)))
+       if (drm_WARN_ON_ONCE(&i915->drm, i >= ARRAY_SIZE(rc6->cur_residency)))
                return 0;
 
        fw_domains = intel_uncore_forcewake_for_reg(uncore, reg, FW_REG_READ);

diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
index bc44fe8..7e2c6ac 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
@@ -568,7 +568,8 @@ static void flush_cs_tlb(struct intel_engine_cs *engine)
                return;
 
        /* ring should be idle before issuing a sync flush*/
-       WARN_ON((ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE) == 0);
+       drm_WARN_ON(&dev_priv->drm,
+                   (ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE) == 0);
 
        ENGINE_WRITE(engine, RING_INSTPM,
                     _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
@@ -1787,8 +1788,8 @@ static void ring_release(struct intel_engine_cs *engine)
 {
        struct drm_i915_private *dev_priv = engine->i915;
 
-       WARN_ON(INTEL_GEN(dev_priv) > 2 &&
-               (ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE) == 0);
+       drm_WARN_ON(&dev_priv->drm, INTEL_GEN(dev_priv) > 2 &&
+                   (ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE) == 0);
 
        intel_engine_cleanup_common(engine);
 

diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
index d2a3d93..30ae29b 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -1026,7 +1026,8 @@ static bool chv_rps_enable(struct intel_rps *rps)
        vlv_punit_put(i915);
 
        /* RPS code assumes GPLL is used */
-       WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
+       drm_WARN_ONCE(&i915->drm, (val & GPLLENABLE) == 0,
+                     "GPLL not enabled\n");
 
        DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
        DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
@@ -1123,7 +1124,8 @@ static bool vlv_rps_enable(struct intel_rps *rps)
        vlv_punit_put(i915);
 
        /* RPS code assumes GPLL is used */
-       WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
+       drm_WARN_ONCE(&i915->drm, (val & GPLLENABLE) == 0,
+                     "GPLL not enabled\n");
 
        DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
        DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
@@ -1191,11 +1193,11 @@ void intel_rps_enable(struct intel_rps *rps)
        if (!rps->enabled)
                return;
 
-       WARN_ON(rps->max_freq < rps->min_freq);
-       WARN_ON(rps->idle_freq > rps->max_freq);
+       drm_WARN_ON(&i915->drm, rps->max_freq < rps->min_freq);
+       drm_WARN_ON(&i915->drm, rps->idle_freq > rps->max_freq);
 
-       WARN_ON(rps->efficient_freq < rps->min_freq);
-       WARN_ON(rps->efficient_freq > rps->max_freq);
+       drm_WARN_ON(&i915->drm, rps->efficient_freq < rps->min_freq);
+       drm_WARN_ON(&i915->drm, rps->efficient_freq > rps->max_freq);
 }
 
 static void gen6_rps_disable(struct intel_rps *rps)
@@ -1390,9 +1392,9 @@ static void chv_rps_init(struct intel_rps *rps)
                        BIT(VLV_IOSF_SB_NC) |
                        BIT(VLV_IOSF_SB_CCK));
 
-       WARN_ONCE((rps->max_freq | rps->efficient_freq | rps->rp1_freq |
-                  rps->min_freq) & 1,
-                 "Odd GPU freq values\n");
+       drm_WARN_ONCE(&i915->drm, (rps->max_freq | rps->efficient_freq |
+                                  rps->rp1_freq | rps->min_freq) & 1,
+                     "Odd GPU freq values\n");
 }
 
 static void vlv_c0_read(struct intel_uncore *uncore, struct intel_rps_ei *ei)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 4e292d4..5a7db27 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -827,7 +827,7 @@ wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
                DRM_WARN("No common index found between subslice mask %x and L3 bank mask %x!\n",
                         intel_sseu_get_subslices(sseu, slice), l3_en);
                subslice = fls(l3_en);
-               WARN_ON(!subslice);
+               drm_WARN_ON(&i915->drm, !subslice);
        }
        subslice--;