arm64: dts: imx8mq-evk: Add spdif sound card support

There are two spdif IP on imx8mq, spdif1 is for normal
spdif device, spdif2 is for HDMI ARC interface.

Enable these spdif sound card in this patch.

Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
index 2418cca..e425081 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
@@ -87,6 +87,21 @@
                        clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>;
                };
        };
+
+       sound-spdif {
+               compatible = "fsl,imx-audio-spdif";
+               model = "imx-spdif";
+               spdif-controller = <&spdif1>;
+               spdif-out;
+               spdif-in;
+       };
+
+       sound-hdmi-arc {
+               compatible = "fsl,imx-audio-spdif";
+               model = "imx-hdmi-arc";
+               spdif-controller = <&spdif2>;
+               spdif-in;
+       };
 };
 
 &A53_0 {
@@ -336,6 +351,22 @@
        status = "okay";
 };
 
+&spdif1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_spdif1>;
+       assigned-clocks = <&clk IMX8MQ_CLK_SPDIF1>;
+       assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
+       assigned-clock-rates = <24576000>;
+       status = "okay";
+};
+
+&spdif2 {
+       assigned-clocks = <&clk IMX8MQ_CLK_SPDIF2>;
+       assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
+       assigned-clock-rates = <24576000>;
+       status = "okay";
+};
+
 &uart1 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_uart1>;
@@ -467,6 +498,13 @@
                >;
        };
 
+       pinctrl_spdif1: spdif1grp {
+               fsl,pins = <
+                       MX8MQ_IOMUXC_SPDIF_TX_SPDIF1_OUT        0xd6
+                       MX8MQ_IOMUXC_SPDIF_RX_SPDIF1_IN         0xd6
+               >;
+       };
+
        pinctrl_uart1: uart1grp {
                fsl,pins = <
                        MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX             0x49

diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index 49cc792..a841a02 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -793,6 +793,30 @@
                        ranges = <0x30800000 0x30800000 0x400000>,
                                 <0x08000000 0x08000000 0x10000000>;
 
+                       spdif1: spdif@30810000 {
+                               compatible = "fsl,imx35-spdif";
+                               reg = <0x30810000 0x10000>;
+                               interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, /* core */
+                                       <&clk IMX8MQ_CLK_25M>, /* rxtx0 */
+                                       <&clk IMX8MQ_CLK_SPDIF1>, /* rxtx1 */
+                                       <&clk IMX8MQ_CLK_DUMMY>, /* rxtx2 */
+                                       <&clk IMX8MQ_CLK_DUMMY>, /* rxtx3 */
+                                       <&clk IMX8MQ_CLK_DUMMY>, /* rxtx4 */
+                                       <&clk IMX8MQ_CLK_IPG_ROOT>, /* rxtx5 */
+                                       <&clk IMX8MQ_CLK_DUMMY>, /* rxtx6 */
+                                       <&clk IMX8MQ_CLK_DUMMY>, /* rxtx7 */
+                                       <&clk IMX8MQ_CLK_DUMMY>; /* spba */
+                               clock-names = "core", "rxtx0",
+                                             "rxtx1", "rxtx2",
+                                             "rxtx3", "rxtx4",
+                                             "rxtx5", "rxtx6",
+                                             "rxtx7", "spba";
+                               dmas = <&sdma1 8 18 0>, <&sdma1 9 18 0>;
+                               dma-names = "rx", "tx";
+                               status = "disabled";
+                       };
+
                        ecspi1: spi@30820000 {
                                #address-cells = <1>;
                                #size-cells = <0>;
@@ -862,6 +886,30 @@
                                status = "disabled";
                        };
 
+                       spdif2: spdif@308a0000 {
+                               compatible = "fsl,imx35-spdif";
+                               reg = <0x308a0000 0x10000>;
+                               interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, /* core */
+                                       <&clk IMX8MQ_CLK_25M>, /* rxtx0 */
+                                       <&clk IMX8MQ_CLK_SPDIF2>, /* rxtx1 */
+                                       <&clk IMX8MQ_CLK_DUMMY>, /* rxtx2 */
+                                       <&clk IMX8MQ_CLK_DUMMY>, /* rxtx3 */
+                                       <&clk IMX8MQ_CLK_DUMMY>, /* rxtx4 */
+                                       <&clk IMX8MQ_CLK_IPG_ROOT>, /* rxtx5 */
+                                       <&clk IMX8MQ_CLK_DUMMY>, /* rxtx6 */
+                                       <&clk IMX8MQ_CLK_DUMMY>, /* rxtx7 */
+                                       <&clk IMX8MQ_CLK_DUMMY>; /* spba */
+                               clock-names = "core", "rxtx0",
+                                             "rxtx1", "rxtx2",
+                                             "rxtx3", "rxtx4",
+                                             "rxtx5", "rxtx6",
+                                             "rxtx7", "spba";
+                               dmas = <&sdma1 16 18 0>, <&sdma1 17 18 0>;
+                               dma-names = "rx", "tx";
+                               status = "disabled";
+                       };
+
                        sai2: sai@308b0000 {
                                #sound-dai-cells = <0>;
                                compatible = "fsl,imx8mq-sai";