octeontx2-af: cn10k: Increase outstanding LMTST transactions
authorPavan Nikhilesh <pbhagavatula@marvell.com>
Tue, 5 Dec 2023 05:52:41 +0000 (11:22 +0530)
committerPaolo Abeni <pabeni@redhat.com>
Wed, 6 Dec 2023 12:37:32 +0000 (13:37 +0100)
Currently the number of outstanding store transactions issued by AP as
a part of LMTST operation is set to 1 i.e default value.
This patch set to max supported value to increase the performance.

Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Signed-off-by: Geetha sowjanya <gakula@marvell.com>
Link: https://lore.kernel.org/r/20231205055241.26355-1-gakula@marvell.com
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
drivers/net/ethernet/marvell/octeontx2/af/rvu.h
drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c
drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h

index 7cd98f0..c1e868a 100644 (file)
@@ -935,6 +935,9 @@ static int rvu_setup_hw_resources(struct rvu *rvu)
        hw->total_vfs = (cfg >> 20) & 0xFFF;
        hw->max_vfs_per_pf = (cfg >> 40) & 0xFF;
 
+       if (!is_rvu_otx2(rvu))
+               rvu_apr_block_cn10k_init(rvu);
+
        /* Init NPA LF's bitmap */
        block = &hw->block[BLKADDR_NPA];
        if (!block->implemented)
index a3de437..814945a 100644 (file)
@@ -969,6 +969,7 @@ void rvu_nix_block_cn10k_init(struct rvu *rvu, struct nix_hw *nix_hw);
 
 /* CN10K RVU - LMT*/
 void rvu_reset_lmt_map_tbl(struct rvu *rvu, u16 pcifunc);
+void rvu_apr_block_cn10k_init(struct rvu *rvu);
 
 #ifdef CONFIG_DEBUG_FS
 void rvu_dbg_init(struct rvu *rvu);
index 0e74c5a..7fa98ae 100644 (file)
@@ -559,3 +559,12 @@ void rvu_nix_block_cn10k_init(struct rvu *rvu, struct nix_hw *nix_hw)
        cfg |= BIT_ULL(1) | BIT_ULL(2);
        rvu_write64(rvu, blkaddr, NIX_AF_CFG, cfg);
 }
+
+void rvu_apr_block_cn10k_init(struct rvu *rvu)
+{
+       u64 reg;
+
+       reg = rvu_read64(rvu, BLKADDR_APR, APR_AF_LMT_CFG);
+       reg |=  FIELD_PREP(LMTST_THROTTLE_MASK, LMTST_WR_PEND_MAX);
+       rvu_write64(rvu, BLKADDR_APR, APR_AF_LMT_CFG, reg);
+}
index b42e631..189f0ea 100644 (file)
 #define APR_LMT_MAP_ENT_DIS_SCH_CMP_SHIFT      23
 #define APR_LMT_MAP_ENT_SCH_ENA_SHIFT          22
 #define APR_LMT_MAP_ENT_DIS_LINE_PREF_SHIFT    21
+#define LMTST_THROTTLE_MASK            GENMASK_ULL(38, 35)
+#define LMTST_WR_PEND_MAX              15
 
 #endif /* RVU_REG_H */