Merge patch series "Add support to handle misaligned accesses in S-mode"

Clément Léger <cleger@rivosinc.com> says:

Since commit 61cadb9 ("Provide new description of misaligned load/store
behavior compatible with privileged architecture.") in the RISC-V ISA
manual, it is stated that misaligned load/store might not be supported.
However, the RISC-V kernel uABI describes that misaligned accesses are
supported. In order to support that, this series adds support for S-mode
handling of misaligned accesses as well support for prctl(PR_UNALIGN).

Handling misaligned access in kernel allows for a finer grain control
of the misaligned accesses behavior, and thanks to the prctl() call,
can allow disabling misaligned access emulation to generate SIGBUS. User
space can then optimize its software by removing such access based on
SIGBUS generation.

This series is useful when using a SBI implementation that does not
handle misaligned traps as well as detecting misaligned accesses
generated by userspace application using the prctrl(PR_SET_UNALIGN)
feature.

This series can be tested using the spike simulator[1] and a modified
openSBI version[2] which allows to always delegate misaligned load/store to
S-mode. A test[3] that exercise various instructions/registers can be
executed to verify the unaligned access support.

[1] https://github.com/riscv-software-src/riscv-isa-sim
[2] https://github.com/rivosinc/opensbi/tree/dev/cleger/no_misaligned
[3] https://github.com/clementleger/unaligned_test

* b4-shazam-merge:
  riscv: add support for PR_SET_UNALIGN and PR_GET_UNALIGN
  riscv: report misaligned accesses emulation to hwprobe
  riscv: annotate check_unaligned_access_boot_cpu() with __init
  riscv: add support for sysctl unaligned_enabled control
  riscv: add floating point insn support to misaligned access emulation
  riscv: report perf event for misaligned fault
  riscv: add support for misaligned trap handling in S-mode
  riscv: remove unused functions in traps_misaligned.c

Link: https://lore.kernel.org/r/20231004151405.521596-1-cleger@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>

diff --cc arch/riscv/Kconfig
Simple merge

diff --cc arch/riscv/include/asm/cpufeature.h
index 13b7d35,e4ae6af..7f1e46a
--- 1/arch/riscv/include/asm/cpufeature.h
--- 2/arch/riscv/include/asm/cpufeature.h
+++ b/arch/riscv/include/asm/cpufeature.h
@@@ -31,6 -31,23 +31,24 @@@ DECLARE_PER_CPU(long, misaligned_access
  extern struct riscv_isainfo hart_isa[NR_CPUS];
  
  void check_unaligned_access(int cpu);
 +void riscv_user_isa_enable(void);
  
+ #ifdef CONFIG_RISCV_MISALIGNED
+ bool unaligned_ctl_available(void);
+ bool check_unaligned_access_emulated(int cpu);
+ void unaligned_emulation_finish(void);
+ #else
+ static inline bool unaligned_ctl_available(void)
+ {
+       return false;
+ }
+ 
+ static inline bool check_unaligned_access_emulated(int cpu)
+ {
+       return false;
+ }
+ 
+ static inline void unaligned_emulation_finish(void) {}
+ #endif
+ 
  #endif

diff --cc arch/riscv/kernel/cpufeature.c
Simple merge

diff --cc arch/riscv/kernel/smpboot.c
Simple merge

diff --cc arch/riscv/kernel/traps.c
Simple merge