drm/amdgpu: correct ih_chicken programming for vega10/vega20 ih blocks

IH_CHICKEN.MC_SPACE_FBPA_ENABLE field is only
valid when IH_RB_CNTL.MC_SPACE is programed to 0x3,
frame buffer physical address. For both bus address
and gpu virtual address, don't program MC_SPACE_FBPA_ENABLE
field

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Dennis Li <Dennis.Li@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
index 6694df7..17c0a07 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
@@ -281,9 +281,6 @@ static int vega10_ih_irq_init(struct amdgpu_device *adev)
                if (adev->irq.ih.use_bus_addr) {
                        ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN,
                                                   MC_SPACE_GPA_ENABLE, 1);
-               } else {
-                       ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN,
-                                                  MC_SPACE_FBPA_ENABLE, 1);
                }
                WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken);
        }

diff --git a/drivers/gpu/drm/amd/amdgpu/vega20_ih.c b/drivers/gpu/drm/amd/amdgpu/vega20_ih.c
index 913b763..e381a25 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/vega20_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/vega20_ih.c
@@ -312,9 +312,6 @@ static int vega20_ih_irq_init(struct amdgpu_device *adev)
                if (adev->irq.ih.use_bus_addr) {
                        ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN,
                                                   MC_SPACE_GPA_ENABLE, 1);
-               } else {
-                       ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN,
-                                                  MC_SPACE_FBPA_ENABLE, 1);
                }
                WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken);
        }