drm/amdgpu: Switch to aca bank for xgmi pcs err cnt
authorHawking Zhang <Hawking.Zhang@amd.com>
Tue, 12 Dec 2023 08:46:30 +0000 (16:46 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 13 Dec 2023 20:28:47 +0000 (15:28 -0500)
Instead of software managed counters.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Yang Wang <kevinyang.wang@amd.com>
Reviewed-by: Stanley.Yang <Stanley.Yang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_mca.h
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

index e51e891..b399f1b 100644 (file)
@@ -46,6 +46,8 @@
 #define MCA_REG__STATUS__ERRORCODEEXT(x)       MCA_REG_FIELD(x, 21, 16)
 #define MCA_REG__STATUS__ERRORCODE(x)          MCA_REG_FIELD(x, 15, 0)
 
+#define MCA_REG__MISC0__ERRCNT(x)              MCA_REG_FIELD(x, 43, 32)
+
 #define MCA_REG__SYND__ERRORINFORMATION(x)     MCA_REG_FIELD(x, 17, 0)
 
 enum amdgpu_mca_ip {
index ddd782f..3998c9b 100644 (file)
@@ -2537,13 +2537,15 @@ static int mca_pcs_xgmi_mca_get_err_count(const struct mca_ras_info *mca_ras, st
                                          uint32_t *count)
 {
        u32 ext_error_code;
+       u32 err_cnt;
 
        ext_error_code = MCA_REG__STATUS__ERRORCODEEXT(entry->regs[MCA_REG_IDX_STATUS]);
+       err_cnt = MCA_REG__MISC0__ERRCNT(entry->regs[MCA_REG_IDX_MISC0]);
 
        if (type == AMDGPU_MCA_ERROR_TYPE_UE && ext_error_code == 0)
-               *count = 1;
+               *count = err_cnt;
        else if (type == AMDGPU_MCA_ERROR_TYPE_CE && ext_error_code == 6)
-               *count = 1;
+               *count = err_cnt;
 
        return 0;
 }