drm/amd/display: Update dummy P-state search to use DCN32 DML

[Why]
Current DCN3.2 logic for finding the dummy P-state index uses the
DCN3.0 DML validation function instead of DCN3.2 DML.

This can result in either unexpected DML VBA values, or unexpected
dummy P-state index to be used.

[How]
Update the dummy P-state logic to use DCN3.2 DML validation function.

Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Reviewed-by: Nevenko Stupar <Nevenko.Stupar@amd.com>
Acked-by: Wayne Lin <wayne.lin@amd.com>
Signed-off-by: George Shen <george.shen@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
index 8e4c9d0..f436869 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
@@ -243,6 +243,50 @@ void dcn32_build_wm_range_table_fpu(struct clk_mgr_internal *clk_mgr)
        clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.max_uclk = 0xFFFF;
 }
 
+/**
+ * Finds dummy_latency_index when MCLK switching using firmware based
+ * vblank stretch is enabled. This function will iterate through the
+ * table of dummy pstate latencies until the lowest value that allows
+ * dm_allow_self_refresh_and_mclk_switch to happen is found
+ */
+int dcn32_find_dummy_latency_index_for_fw_based_mclk_switch(struct dc *dc,
+                                                           struct dc_state *context,
+                                                           display_e2e_pipe_params_st *pipes,
+                                                           int pipe_cnt,
+                                                           int vlevel)
+{
+       const int max_latency_table_entries = 4;
+       const struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
+       int dummy_latency_index = 0;
+
+       dc_assert_fp_enabled();
+
+       while (dummy_latency_index < max_latency_table_entries) {
+               context->bw_ctx.dml.soc.dram_clock_change_latency_us =
+                               dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us;
+               dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, false);
+
+               if (vlevel < context->bw_ctx.dml.vba.soc.num_states &&
+                               vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] != dm_dram_clock_change_unsupported)
+                       break;
+
+               dummy_latency_index++;
+       }
+
+       if (dummy_latency_index == max_latency_table_entries) {
+               ASSERT(dummy_latency_index != max_latency_table_entries);
+               /* If the execution gets here, it means dummy p_states are
+                * not possible. This should never happen and would mean
+                * something is severely wrong.
+                * Here we reset dummy_latency_index to 3, because it is
+                * better to have underflows than system crashes.
+                */
+               dummy_latency_index = max_latency_table_entries - 1;
+       }
+
+       return dummy_latency_index;
+}
+
 /**
  * dcn32_helper_populate_phantom_dlg_params - Get DLG params for phantom pipes
  * and populate pipe_ctx with those params.
@@ -1646,7 +1690,7 @@ void dcn32_calculate_wm_and_dlg_fpu(struct dc *dc, struct dc_state *context,
                        dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch(dc, context);
 
                if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) {
-                       dummy_latency_index = dcn30_find_dummy_latency_index_for_fw_based_mclk_switch(dc,
+                       dummy_latency_index = dcn32_find_dummy_latency_index_for_fw_based_mclk_switch(dc,
                                context, pipes, pipe_cnt, vlevel);
 
                        /* After calling dcn30_find_dummy_latency_index_for_fw_based_mclk_switch

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.h b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.h
index 3ed06ab..6ce2210 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.h
@@ -71,4 +71,10 @@ void dcn32_calculate_wm_and_dlg_fpu(struct dc *dc, struct dc_state *context,
 
 void dcn32_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params);
 
+int dcn32_find_dummy_latency_index_for_fw_based_mclk_switch(struct dc *dc,
+                                                           struct dc_state *context,
+                                                           display_e2e_pipe_params_st *pipes,
+                                                           int pipe_cnt,
+                                                           int vlevel);
+
 #endif