drm/amdgpu: store the mall size in the gmc structure
authorAlex Deucher <alexander.deucher@amd.com>
Thu, 31 Mar 2022 22:11:51 +0000 (18:11 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Thu, 28 Apr 2022 21:47:16 +0000 (17:47 -0400)
This will be useful in future patches.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c

index 032b031..67e488c 100644 (file)
@@ -257,6 +257,9 @@ struct amdgpu_gmc {
        struct amdgpu_bo                *pdb0_bo;
        /* CPU kmapped address of pdb0*/
        void                            *ptr_pdb0;
+
+       /* MALL size */
+       u64 mall_size;
 };
 
 #define amdgpu_gmc_flush_gpu_tlb(adev, vmid, vmhub, type) ((adev)->gmc.gmc_funcs->flush_gpu_tlb((adev), (vmid), (vmhub), (type)))
index 20946bc..487c339 100644 (file)
@@ -883,6 +883,24 @@ static int gmc_v10_0_sw_init(void *handle)
                adev->gmc.vram_vendor = vram_vendor;
        }
 
+       switch (adev->ip_versions[GC_HWIP][0]) {
+       case IP_VERSION(10, 3, 0):
+               adev->gmc.mall_size = 128 * 1024 * 1024;
+               break;
+       case IP_VERSION(10, 3, 2):
+               adev->gmc.mall_size = 96 * 1024 * 1024;
+               break;
+       case IP_VERSION(10, 3, 4):
+               adev->gmc.mall_size = 32 * 1024 * 1024;
+               break;
+       case IP_VERSION(10, 3, 5):
+               adev->gmc.mall_size = 16 * 1024 * 1024;
+               break;
+       default:
+               adev->gmc.mall_size = 0;
+               break;
+       }
+
        switch (adev->ip_versions[GC_HWIP][0]) {
        case IP_VERSION(10, 1, 10):
        case IP_VERSION(10, 1, 1):