arm64: dts: qcom: add sm8250 GPU nodes

This brings up the GPU. Tested on HDK865 by running vulkan CTS.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Link: https://lore.kernel.org/r/20200709135251.643-15-jonathan@marek.ca
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index 551a3ce..377172e 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -1047,6 +1047,148 @@
                        #hwlock-cells = <1>;
                };
 
+               gpu: gpu@3d00000 {
+                       /*
+                        * note: the amd,imageon compatible makes it possible
+                        * to use the drm/msm driver without the display node,
+                        * make sure to remove it when display node is added
+                        */
+                       compatible = "qcom,adreno-650.2",
+                                    "qcom,adreno",
+                                    "amd,imageon";
+                       #stream-id-cells = <16>;
+
+                       reg = <0 0x03d00000 0 0x40000>;
+                       reg-names = "kgsl_3d0_reg_memory";
+
+                       interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
+
+                       iommus = <&adreno_smmu 0 0x401>;
+
+                       operating-points-v2 = <&gpu_opp_table>;
+
+                       qcom,gmu = <&gmu>;
+
+                       zap-shader {
+                               memory-region = <&gpu_mem>;
+                       };
+
+                       /* note: downstream checks gpu binning for 670 Mhz */
+                       gpu_opp_table: opp-table {
+                               compatible = "operating-points-v2";
+
+                               opp-670000000 {
+                                       opp-hz = /bits/ 64 <670000000>;
+                                       opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+                               };
+
+                               opp-587000000 {
+                                       opp-hz = /bits/ 64 <587000000>;
+                                       opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+                               };
+
+                               opp-525000000 {
+                                       opp-hz = /bits/ 64 <525000000>;
+                                       opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
+                               };
+
+                               opp-490000000 {
+                                       opp-hz = /bits/ 64 <490000000>;
+                                       opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+                               };
+
+                               opp-441600000 {
+                                       opp-hz = /bits/ 64 <441600000>;
+                                       opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
+                               };
+
+                               opp-400000000 {
+                                       opp-hz = /bits/ 64 <400000000>;
+                                       opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+                               };
+
+                               opp-305000000 {
+                                       opp-hz = /bits/ 64 <305000000>;
+                                       opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+                               };
+                       };
+               };
+
+               gmu: gmu@3d6a000 {
+                       compatible="qcom,adreno-gmu-650.2", "qcom,adreno-gmu";
+
+                       reg = <0 0x03d6a000 0 0x30000>,
+                             <0 0x3de0000 0 0x10000>,
+                             <0 0xb290000 0 0x10000>,
+                             <0 0xb490000 0 0x10000>;
+                       reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq";
+
+                       interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "hfi", "gmu";
+
+                       clocks = <&gpucc 0>,
+                                <&gpucc 3>,
+                                <&gpucc 6>,
+                                <&gcc GCC_DDRSS_GPU_AXI_CLK>,
+                                <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
+                       clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
+
+                       power-domains = <&gpucc 0>,
+                                       <&gpucc 1>;
+                       power-domain-names = "cx", "gx";
+
+                       iommus = <&adreno_smmu 5 0x400>;
+
+                       operating-points-v2 = <&gmu_opp_table>;
+
+                       gmu_opp_table: opp-table {
+                               compatible = "operating-points-v2";
+
+                               opp-200000000 {
+                                       opp-hz = /bits/ 64 <200000000>;
+                                       opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
+                               };
+                       };
+               };
+
+               gpucc: clock-controller@3d90000 {
+                       compatible = "qcom,sm8250-gpucc";
+                       reg = <0 0x03d90000 0 0x9000>;
+                       clocks = <&rpmhcc RPMH_CXO_CLK>,
+                                <&gcc GCC_GPU_GPLL0_CLK_SRC>,
+                                <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
+                       clock-names = "bi_tcxo",
+                                     "gcc_gpu_gpll0_clk_src",
+                                     "gcc_gpu_gpll0_div_clk_src";
+                       #clock-cells = <1>;
+                       #reset-cells = <1>;
+                       #power-domain-cells = <1>;
+               };
+
+               adreno_smmu: iommu@3da0000 {
+                       compatible = "qcom,sm8250-smmu-500", "arm,mmu-500";
+                       reg = <0 0x03da0000 0 0x10000>;
+                       #iommu-cells = <2>;
+                       #global-interrupts = <2>;
+                       interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&gpucc 0>,
+                                <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+                                <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
+                       clock-names = "ahb", "bus", "iface";
+
+                       power-domains = <&gpucc 0>;
+               };
+
                slpi: remoteproc@5c00000 {
                        compatible = "qcom,sm8250-slpi-pas";
                        reg = <0 0x05c00000 0 0x4000>;