drm/i915/dg1: Add DPLL macros for DG1

DG1 has 4 DPLLs where DPLL0 and DPLL1 drive DDIA/B and
DPLL2 and DPLL3 drive DDI-TC1/DDI-TC2.

Introduce DG1_DPLL_CFCRx() helper macros to configure
DPLL registers.

Bspec: 50288, 50299

Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20201014191937.1266226-4-lucas.demarchi@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index 5d9a2bc..205542f 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -154,6 +154,23 @@ enum intel_dpll_id {
         * @DPLL_ID_TGL_MGPLL6: TGL TC PLL port 6 (TC6)
         */
        DPLL_ID_TGL_MGPLL6 = 8,
+
+       /**
+        * @DPLL_ID_DG1_DPLL0: DG1 combo PHY DPLL0
+        */
+       DPLL_ID_DG1_DPLL0 = 0,
+       /**
+        * @DPLL_ID_DG1_DPLL1: DG1 combo PHY DPLL1
+        */
+       DPLL_ID_DG1_DPLL1 = 1,
+       /**
+        * @DPLL_ID_DG1_DPLL2: DG1 combo PHY DPLL2
+        */
+       DPLL_ID_DG1_DPLL2 = 2,
+       /**
+        * @DPLL_ID_DG1_DPLL3: DG1 combo PHY DPLL3
+        */
+       DPLL_ID_DG1_DPLL3 = 3,
 };
 
 #define I915_NUM_PLLS 9

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 04c966a..0b67c86 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -242,7 +242,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define _MMIO_PIPE3(pipe, a, b, c)     _MMIO(_PICK(pipe, a, b, c))
 #define _MMIO_PORT3(pipe, a, b, c)     _MMIO(_PICK(pipe, a, b, c))
 #define _MMIO_PHY3(phy, a, b, c)       _MMIO(_PHY3(phy, a, b, c))
-#define _MMIO_PLL3(pll, a, b, c)       _MMIO(_PICK(pll, a, b, c))
+#define _MMIO_PLL3(pll, ...)           _MMIO(_PICK(pll, __VA_ARGS__))
+
 
 /*
  * Device info offset array based helpers for groups of registers with unevenly
@@ -10531,6 +10532,20 @@ enum skl_power_gate {
 #define RKL_DPLL_CFGCR1(pll)           _MMIO_PLL(pll, _TGL_DPLL0_CFGCR1, \
                                                  _TGL_DPLL1_CFGCR1)
 
+#define _DG1_DPLL2_CFGCR0              0x16C284
+#define _DG1_DPLL3_CFGCR0              0x16C28C
+#define DG1_DPLL_CFGCR0(pll)           _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \
+                                                  _TGL_DPLL1_CFGCR0, \
+                                                  _DG1_DPLL2_CFGCR0, \
+                                                  _DG1_DPLL3_CFGCR0)
+
+#define _DG1_DPLL2_CFGCR1               0x16C288
+#define _DG1_DPLL3_CFGCR1               0x16C290
+#define DG1_DPLL_CFGCR1(pll)            _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \
+                                                  _TGL_DPLL1_CFGCR1, \
+                                                  _DG1_DPLL2_CFGCR1, \
+                                                  _DG1_DPLL3_CFGCR1)
+
 #define _DKL_PHY1_BASE                 0x168000
 #define _DKL_PHY2_BASE                 0x169000
 #define _DKL_PHY3_BASE                 0x16A000