KVM: arm64: Set ID_AA64DFR0_EL1.PMUVer to 0 when no PMU support

We always expose the HW view of PMU in ID_AA64FDR0_EL1.PMUver,
even when the PMU feature is disabled, while the architecture
says that FEAT_PMUv3 not being implemented should result in this
field being zero.

Let's follow the architecture's guidance.

Reviewed-by: Alexandru Elisei <alexandru.elisei@arm.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>

diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index d2e1d74..6629cfd 100644 (file)
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -1070,10 +1070,15 @@ static u64 read_id_reg(const struct kvm_vcpu *vcpu,
                         (0xfUL << ID_AA64ISAR1_GPA_SHIFT) |
                         (0xfUL << ID_AA64ISAR1_GPI_SHIFT));
        } else if (id == SYS_ID_AA64DFR0_EL1) {
+               u64 cap = 0;
+
                /* Limit guests to PMUv3 for ARMv8.1 */
+               if (kvm_vcpu_has_pmu(vcpu))
+                       cap = ID_AA64DFR0_PMUVER_8_1;
+
                val = cpuid_feature_cap_perfmon_field(val,
                                                ID_AA64DFR0_PMUVER_SHIFT,
-                                               ID_AA64DFR0_PMUVER_8_1);
+                                               cap);
        } else if (id == SYS_ID_DFR0_EL1) {
                /* Limit guests to PMUv3 for ARMv8.1 */
                val = cpuid_feature_cap_perfmon_field(val,