arm64: dts: qcom: sdm845: Drop flags for mdss irqs

The number of interrupt cells for the mdss interrupt controller is 1,
meaning there should only be one cell for the interrupt number, not two.
Drop the second cell containing (unused) irq flags.

Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Fixes: 08c2a076d18f ("arm64: dts: qcom: sdm845: Add dpu to sdm845 dts file")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220302225411.2456001-4-dmitry.baryshkov@linaro.org

diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index a49376d..692cf4b 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -4283,7 +4283,7 @@
                                power-domains = <&rpmhpd SDM845_CX>;
 
                                interrupt-parent = <&mdss>;
-                               interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
+                               interrupts = <0>;
 
                                ports {
                                        #address-cells = <1>;
@@ -4335,7 +4335,7 @@
                                reg-names = "dsi_ctrl";
 
                                interrupt-parent = <&mdss>;
-                               interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
+                               interrupts = <4>;
 
                                clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
                                         <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
@@ -4407,7 +4407,7 @@
                                reg-names = "dsi_ctrl";
 
                                interrupt-parent = <&mdss>;
-                               interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
+                               interrupts = <5>;
 
                                clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
                                         <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,