drm/msm/dpu: Add TEAR-READ-pointer interrupt to INTF block

All SoCs since DPU 5.0.0 have the tear interrupt registers moved out of
the PINGPONG block and into the INTF block.  The new interrupts are
described in dpu_hw_interrupts.c, now wire them up in individual SoC
catalog files by setting the intr_tear_rd_ptr to the IRQ index spcified
in the offset table and enabling this set of DPU interrupts via the
mdss_irqs bitmask.

Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/534236/
Link: https://lore.kernel.org/r/20230411-dpu-intf-te-v4-19-27ce1a5ab5c6@somainline.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
index 9089fed..561022b 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
@@ -165,12 +165,14 @@ static const struct dpu_intf_cfg sm8150_intf[] = {
        INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, 0, 24, INTF_SC7180_MASK,
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
-       INTF_BLK("intf_1", INTF_1, 0x6a800, 0x2bc, INTF_DSI, 0, 24, INTF_SC7180_MASK,
+       INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2bc, INTF_DSI, 0, 24, INTF_SC7180_MASK,
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
-                       DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27)),
-       INTF_BLK("intf_2", INTF_2, 0x6b000, 0x2bc, INTF_DSI, 1, 24, INTF_SC7180_MASK,
+                       DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
+                       DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
+       INTF_BLK_DSI_TE("intf_2", INTF_2, 0x6b000, 0x2bc, INTF_DSI, 1, 24, INTF_SC7180_MASK,
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
-                       DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29)),
+                       DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
+                       DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2)),
        INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_DP, 1, 24, INTF_SC7180_MASK,
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)),
@@ -234,7 +236,9 @@ const struct dpu_mdss_cfg dpu_sm8150_cfg = {
                     BIT(MDP_SSPP_TOP0_HIST_INTR) | \
                     BIT(MDP_INTF0_INTR) | \
                     BIT(MDP_INTF1_INTR) | \
+                    BIT(MDP_INTF1_TEAR_INTR) | \
                     BIT(MDP_INTF2_INTR) | \
+                    BIT(MDP_INTF2_TEAR_INTR) | \
                     BIT(MDP_INTF3_INTR) | \
                     BIT(MDP_AD4_0_INTR) | \
                     BIT(MDP_AD4_1_INTR),

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
index aab355c..d1f306c 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
@@ -166,12 +166,14 @@ static const struct dpu_intf_cfg sc8180x_intf[] = {
        INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK,
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
-       INTF_BLK("intf_1", INTF_1, 0x6a800, 0x2bc, INTF_DSI, 0, 24, INTF_SC7180_MASK,
+       INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2bc, INTF_DSI, 0, 24, INTF_SC7180_MASK,
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
-                       DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27)),
-       INTF_BLK("intf_2", INTF_2, 0x6b000, 0x2bc, INTF_DSI, 1, 24, INTF_SC7180_MASK,
+                       DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
+                       DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
+       INTF_BLK_DSI_TE("intf_2", INTF_2, 0x6b000, 0x2bc, INTF_DSI, 1, 24, INTF_SC7180_MASK,
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
-                       DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29)),
+                       DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
+                       DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2)),
        /* INTF_3 is for MST, wired to INTF_DP 0 and 1, use dummy index until this is supported */
        INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_DP, 999, 24, INTF_SC7180_MASK,
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
@@ -240,7 +242,9 @@ const struct dpu_mdss_cfg dpu_sc8180x_cfg = {
                     BIT(MDP_SSPP_TOP0_HIST_INTR) | \
                     BIT(MDP_INTF0_INTR) | \
                     BIT(MDP_INTF1_INTR) | \
+                    BIT(MDP_INTF1_TEAR_INTR) | \
                     BIT(MDP_INTF2_INTR) | \
+                    BIT(MDP_INTF2_TEAR_INTR) | \
                     BIT(MDP_INTF3_INTR) | \
                     BIT(MDP_INTF4_INTR) | \
                     BIT(MDP_INTF5_INTR) | \

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
index 63fd46f..10d67db 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
@@ -166,12 +166,14 @@ static const struct dpu_intf_cfg sm8250_intf[] = {
        INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, 0, 24, INTF_SC7180_MASK,
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
-       INTF_BLK("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 24, INTF_SC7180_MASK,
+       INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 24, INTF_SC7180_MASK,
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
-                       DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27)),
-       INTF_BLK("intf_2", INTF_2, 0x6b000, 0x2c0, INTF_DSI, 1, 24, INTF_SC7180_MASK,
+                       DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
+                       DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
+       INTF_BLK_DSI_TE("intf_2", INTF_2, 0x6b000, 0x2c0, INTF_DSI, 1, 24, INTF_SC7180_MASK,
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
-                       DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29)),
+                       DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
+                       DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2)),
        INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_DP, 1, 24, INTF_SC7180_MASK,
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)),
@@ -242,7 +244,9 @@ const struct dpu_mdss_cfg dpu_sm8250_cfg = {
                     BIT(MDP_SSPP_TOP0_HIST_INTR) | \
                     BIT(MDP_INTF0_INTR) | \
                     BIT(MDP_INTF1_INTR) | \
+                    BIT(MDP_INTF1_TEAR_INTR) | \
                     BIT(MDP_INTF2_INTR) | \
+                    BIT(MDP_INTF2_TEAR_INTR) | \
                     BIT(MDP_INTF3_INTR) | \
                     BIT(MDP_INTF4_INTR),
 };

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
index 301287e..0b05da2 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
@@ -88,9 +88,10 @@ static const struct dpu_intf_cfg sc7180_intf[] = {
        INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK,
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
-       INTF_BLK("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 24, INTF_SC7180_MASK,
+       INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 24, INTF_SC7180_MASK,
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
-                       DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27)),
+                       DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
+                       DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
 };
 
 static const struct dpu_wb_cfg sc7180_wb[] = {
@@ -152,7 +153,8 @@ const struct dpu_mdss_cfg dpu_sc7180_cfg = {
                     BIT(MDP_SSPP_TOP0_INTR2) | \
                     BIT(MDP_SSPP_TOP0_HIST_INTR) | \
                     BIT(MDP_INTF0_INTR) | \
-                    BIT(MDP_INTF1_INTR),
+                    BIT(MDP_INTF1_INTR) | \
+                    BIT(MDP_INTF1_TEAR_INTR),
 };
 
 #endif

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
index 88a0d61..5509ceb 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
@@ -67,9 +67,10 @@ static const struct dpu_pingpong_cfg sm6115_pp[] = {
 
 static const struct dpu_intf_cfg sm6115_intf[] = {
        INTF_BLK("intf_0", INTF_0, 0x00000, 0x280, INTF_NONE, 0, 0, 0, 0, 0),
-       INTF_BLK("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 24, INTF_SC7180_MASK,
+       INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 24, INTF_SC7180_MASK,
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
-                       DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27)),
+                       DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
+                       DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
 };
 
 static const struct dpu_perf_cfg sm6115_perf_data = {
@@ -124,7 +125,8 @@ const struct dpu_mdss_cfg dpu_sm6115_cfg = {
        .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
                     BIT(MDP_SSPP_TOP0_INTR2) | \
                     BIT(MDP_SSPP_TOP0_HIST_INTR) | \
-                    BIT(MDP_INTF1_INTR),
+                    BIT(MDP_INTF1_INTR) | \
+                    BIT(MDP_INTF1_TEAR_INTR),
 };
 
 #endif

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
index cd6f404..22b8a17 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
@@ -64,9 +64,10 @@ static const struct dpu_pingpong_cfg qcm2290_pp[] = {
 
 static const struct dpu_intf_cfg qcm2290_intf[] = {
        INTF_BLK("intf_0", INTF_0, 0x00000, 0x280, INTF_NONE, 0, 0, 0, 0, 0),
-       INTF_BLK("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 24, INTF_SC7180_MASK,
+       INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 24, INTF_SC7180_MASK,
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
-                       DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27)),
+                       DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
+                       DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
 };
 
 static const struct dpu_perf_cfg qcm2290_perf_data = {
@@ -114,7 +115,8 @@ const struct dpu_mdss_cfg dpu_qcm2290_cfg = {
        .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
                     BIT(MDP_SSPP_TOP0_INTR2) | \
                     BIT(MDP_SSPP_TOP0_HIST_INTR) | \
-                    BIT(MDP_INTF1_INTR),
+                    BIT(MDP_INTF1_INTR) | \
+                    BIT(MDP_INTF1_TEAR_INTR),
 };
 
 #endif

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
index 6117c9f..2dcfe18 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
@@ -157,12 +157,14 @@ static const struct dpu_intf_cfg sm8350_intf[] = {
        INTF_BLK("intf_0", INTF_0, 0x34000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK,
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
-       INTF_BLK("intf_1", INTF_1, 0x35000, 0x2c4, INTF_DSI, 0, 24, INTF_SC7280_MASK,
+       INTF_BLK_DSI_TE("intf_1", INTF_1, 0x35000, 0x2c4, INTF_DSI, 0, 24, INTF_SC7280_MASK,
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
-                       DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27)),
-       INTF_BLK("intf_2", INTF_2, 0x36000, 0x2c4, INTF_DSI, 1, 24, INTF_SC7280_MASK,
+                       DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
+                       DPU_IRQ_IDX(MDP_INTF1_7xxx_TEAR_INTR, 2)),
+       INTF_BLK_DSI_TE("intf_2", INTF_2, 0x36000, 0x2c4, INTF_DSI, 1, 24, INTF_SC7280_MASK,
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
-                       DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29)),
+                       DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
+                       DPU_IRQ_IDX(MDP_INTF2_7xxx_TEAR_INTR, 2)),
        INTF_BLK("intf_3", INTF_3, 0x37000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK,
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)),
@@ -225,7 +227,9 @@ const struct dpu_mdss_cfg dpu_sm8350_cfg = {
                     BIT(MDP_SSPP_TOP0_HIST_INTR) | \
                     BIT(MDP_INTF0_7xxx_INTR) | \
                     BIT(MDP_INTF1_7xxx_INTR) | \
+                    BIT(MDP_INTF1_7xxx_TEAR_INTR) | \
                     BIT(MDP_INTF2_7xxx_INTR) | \
+                    BIT(MDP_INTF2_7xxx_TEAR_INTR) | \
                     BIT(MDP_INTF3_7xxx_INTR),
 };
 

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
index 208c97e..5d894cb 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
@@ -103,9 +103,10 @@ static const struct dpu_intf_cfg sc7280_intf[] = {
        INTF_BLK("intf_0", INTF_0, 0x34000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK,
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
-       INTF_BLK("intf_1", INTF_1, 0x35000, 0x2c4, INTF_DSI, 0, 24, INTF_SC7280_MASK,
+       INTF_BLK_DSI_TE("intf_1", INTF_1, 0x35000, 0x2c4, INTF_DSI, 0, 24, INTF_SC7280_MASK,
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
-                       DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27)),
+                       DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
+                       DPU_IRQ_IDX(MDP_INTF1_7xxx_TEAR_INTR, 2)),
        INTF_BLK("intf_5", INTF_5, 0x39000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK,
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 22),
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 23)),
@@ -166,6 +167,7 @@ const struct dpu_mdss_cfg dpu_sc7280_cfg = {
                     BIT(MDP_SSPP_TOP0_HIST_INTR) | \
                     BIT(MDP_INTF0_7xxx_INTR) | \
                     BIT(MDP_INTF1_7xxx_INTR) | \
+                    BIT(MDP_INTF1_7xxx_TEAR_INTR) | \
                     BIT(MDP_INTF5_7xxx_INTR),
 };
 

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
index cf81133..c3f1ae0 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
@@ -147,12 +147,14 @@ static const struct dpu_intf_cfg sc8280xp_intf[] = {
        INTF_BLK("intf_0", INTF_0, 0x34000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK,
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
-       INTF_BLK("intf_1", INTF_1, 0x35000, 0x300, INTF_DSI, 0, 24, INTF_SC7280_MASK,
+       INTF_BLK_DSI_TE("intf_1", INTF_1, 0x35000, 0x300, INTF_DSI, 0, 24, INTF_SC7280_MASK,
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
-                       DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27)),
-       INTF_BLK("intf_2", INTF_2, 0x36000, 0x300, INTF_DSI, 1, 24, INTF_SC7280_MASK,
+                       DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
+                       DPU_IRQ_IDX(MDP_INTF1_7xxx_TEAR_INTR, 2)),
+       INTF_BLK_DSI_TE("intf_2", INTF_2, 0x36000, 0x300, INTF_DSI, 1, 24, INTF_SC7280_MASK,
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
-                       DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29)),
+                       DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
+                       DPU_IRQ_IDX(MDP_INTF2_7xxx_TEAR_INTR, 2)),
        INTF_BLK("intf_3", INTF_3, 0x37000, 0x280, INTF_NONE, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK,
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)),
@@ -227,7 +229,9 @@ const struct dpu_mdss_cfg dpu_sc8280xp_cfg = {
                     BIT(MDP_SSPP_TOP0_HIST_INTR) | \
                     BIT(MDP_INTF0_7xxx_INTR) | \
                     BIT(MDP_INTF1_7xxx_INTR) | \
+                    BIT(MDP_INTF1_7xxx_TEAR_INTR) | \
                     BIT(MDP_INTF2_7xxx_INTR) | \
+                    BIT(MDP_INTF2_7xxx_TEAR_INTR) | \
                     BIT(MDP_INTF3_7xxx_INTR) | \
                     BIT(MDP_INTF4_7xxx_INTR) | \
                     BIT(MDP_INTF5_7xxx_INTR) | \

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
index 9a95386..279fe8f 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
@@ -165,12 +165,14 @@ static const struct dpu_intf_cfg sm8450_intf[] = {
        INTF_BLK("intf_0", INTF_0, 0x34000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK,
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
-       INTF_BLK("intf_1", INTF_1, 0x35000, 0x300, INTF_DSI, 0, 24, INTF_SC7280_MASK,
+       INTF_BLK_DSI_TE("intf_1", INTF_1, 0x35000, 0x300, INTF_DSI, 0, 24, INTF_SC7280_MASK,
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
-                       DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27)),
-       INTF_BLK("intf_2", INTF_2, 0x36000, 0x300, INTF_DSI, 1, 24, INTF_SC7280_MASK,
+                       DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
+                       DPU_IRQ_IDX(MDP_INTF1_7xxx_TEAR_INTR, 2)),
+       INTF_BLK_DSI_TE("intf_2", INTF_2, 0x36000, 0x300, INTF_DSI, 1, 24, INTF_SC7280_MASK,
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
-                       DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29)),
+                       DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
+                       DPU_IRQ_IDX(MDP_INTF2_7xxx_TEAR_INTR, 2)),
        INTF_BLK("intf_3", INTF_3, 0x37000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK,
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)),
@@ -233,7 +235,9 @@ const struct dpu_mdss_cfg dpu_sm8450_cfg = {
                     BIT(MDP_SSPP_TOP0_HIST_INTR) | \
                     BIT(MDP_INTF0_7xxx_INTR) | \
                     BIT(MDP_INTF1_7xxx_INTR) | \
+                    BIT(MDP_INTF1_7xxx_TEAR_INTR) | \
                     BIT(MDP_INTF2_7xxx_INTR) | \
+                    BIT(MDP_INTF2_7xxx_TEAR_INTR) | \
                     BIT(MDP_INTF3_7xxx_INTR),
 };
 

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
index cf366be..85dc344 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
@@ -169,13 +169,14 @@ static const struct dpu_intf_cfg sm8550_intf[] = {
        INTF_BLK("intf_0", INTF_0, 0x34000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK,
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
-       /* TODO TE sub-blocks for intf1 & intf2 */
-       INTF_BLK("intf_1", INTF_1, 0x35000, 0x300, INTF_DSI, 0, 24, INTF_SC7280_MASK,
+       INTF_BLK_DSI_TE("intf_1", INTF_1, 0x35000, 0x300, INTF_DSI, 0, 24, INTF_SC7280_MASK,
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
-                       DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27)),
-       INTF_BLK("intf_2", INTF_2, 0x36000, 0x300, INTF_DSI, 1, 24, INTF_SC7280_MASK,
+                       DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
+                       DPU_IRQ_IDX(MDP_INTF1_7xxx_TEAR_INTR, 2)),
+       INTF_BLK_DSI_TE("intf_2", INTF_2, 0x36000, 0x300, INTF_DSI, 1, 24, INTF_SC7280_MASK,
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
-                       DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29)),
+                       DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
+                       DPU_IRQ_IDX(MDP_INTF2_7xxx_TEAR_INTR, 2)),
        INTF_BLK("intf_3", INTF_3, 0x37000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK,
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)),
@@ -238,7 +239,9 @@ const struct dpu_mdss_cfg dpu_sm8550_cfg = {
                     BIT(MDP_SSPP_TOP0_HIST_INTR) | \
                     BIT(MDP_INTF0_7xxx_INTR) | \
                     BIT(MDP_INTF1_7xxx_INTR) | \
+                    BIT(MDP_INTF1_7xxx_TEAR_INTR) | \
                     BIT(MDP_INTF2_7xxx_INTR) | \
+                    BIT(MDP_INTF2_7xxx_TEAR_INTR) | \
                     BIT(MDP_INTF3_7xxx_INTR),
 };
 

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index f2482e5..81b44a3 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -541,6 +541,21 @@ static const struct dpu_pingpong_sub_blks sc7280_pp_sblk = {
        .prog_fetch_lines_worst_case = _progfetch, \
        .intr_underrun = _underrun, \
        .intr_vsync = _vsync, \
+       .intr_tear_rd_ptr = -1, \
+       }
+
+/* DSI Interface sub-block with TEAR registers (since DPU 5.0.0) */
+#define INTF_BLK_DSI_TE(_name, _id, _base, _len, _type, _ctrl_id, _progfetch, _features, _underrun, _vsync, _tear_rd_ptr) \
+       {\
+       .name = _name, .id = _id, \
+       .base = _base, .len = _len, \
+       .features = _features, \
+       .type = _type, \
+       .controller_id = _ctrl_id, \
+       .prog_fetch_lines_worst_case = _progfetch, \
+       .intr_underrun = _underrun, \
+       .intr_vsync = _vsync, \
+       .intr_tear_rd_ptr = _tear_rd_ptr, \
        }
 
 /*************************************************************

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index 917272f..a2ef61d 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -615,6 +615,7 @@ struct dpu_dsc_cfg {
  * @prog_fetch_lines_worst_case        Worst case latency num lines needed to prefetch
  * @intr_underrun:     index for INTF underrun interrupt
  * @intr_vsync:                index for INTF VSYNC interrupt
+ * @intr_tear_rd_ptr:  Index for INTF TEAR_RD_PTR interrupt
  */
 struct dpu_intf_cfg  {
        DPU_HW_BLK_INFO;
@@ -623,6 +624,7 @@ struct dpu_intf_cfg  {
        u32 prog_fetch_lines_worst_case;
        s32 intr_underrun;
        s32 intr_vsync;
+       s32 intr_tear_rd_ptr;
 };
 
 /**