MIPS: mscc: ocelot: disable all switch ports by default

The ocelot switch driver used to ignore ports which do not have a
phy-handle property and not probe those, but this is not quite ok since
it is valid to not have a phy-handle property if there is a fixed-link.

It seems that checking for a phy-handle was a proxy for the proper check
which is for the status, but that doesn't make a lot of sense, since the
ocelot driver already iterates using for_each_available_child_of_node
which skips the disabled ports, so I have no idea.

Anyway, a widespread pattern in device trees is for a SoC dtsi to
disable by default all hardware, and let board dts files enable what is
used. So let's do that and enable only the ports with a phy-handle in
the pcb120 and pcb123 device tree files.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>

diff --git a/arch/mips/boot/dts/mscc/ocelot.dtsi b/arch/mips/boot/dts/mscc/ocelot.dtsi
index 535a982..e51db65 100644 (file)
--- a/arch/mips/boot/dts/mscc/ocelot.dtsi
+++ b/arch/mips/boot/dts/mscc/ocelot.dtsi
@@ -150,36 +150,47 @@
 
                                port0: port@0 {
                                        reg = <0>;
+                                       status = "disabled";
                                };
                                port1: port@1 {
                                        reg = <1>;
+                                       status = "disabled";
                                };
                                port2: port@2 {
                                        reg = <2>;
+                                       status = "disabled";
                                };
                                port3: port@3 {
                                        reg = <3>;
+                                       status = "disabled";
                                };
                                port4: port@4 {
                                        reg = <4>;
+                                       status = "disabled";
                                };
                                port5: port@5 {
                                        reg = <5>;
+                                       status = "disabled";
                                };
                                port6: port@6 {
                                        reg = <6>;
+                                       status = "disabled";
                                };
                                port7: port@7 {
                                        reg = <7>;
+                                       status = "disabled";
                                };
                                port8: port@8 {
                                        reg = <8>;
+                                       status = "disabled";
                                };
                                port9: port@9 {
                                        reg = <9>;
+                                       status = "disabled";
                                };
                                port10: port@10 {
                                        reg = <10>;
+                                       status = "disabled";
                                };
                        };
                };

diff --git a/arch/mips/boot/dts/mscc/ocelot_pcb120.dts b/arch/mips/boot/dts/mscc/ocelot_pcb120.dts
index 897de50..d2dc6b3 100644 (file)
--- a/arch/mips/boot/dts/mscc/ocelot_pcb120.dts
+++ b/arch/mips/boot/dts/mscc/ocelot_pcb120.dts
@@ -69,40 +69,48 @@
 };
 
 &port0 {
+       status = "okay";
        phy-handle = <&phy0>;
 };
 
 &port1 {
+       status = "okay";
        phy-handle = <&phy1>;
 };
 
 &port2 {
+       status = "okay";
        phy-handle = <&phy2>;
 };
 
 &port3 {
+       status = "okay";
        phy-handle = <&phy3>;
 };
 
 &port4 {
+       status = "okay";
        phy-handle = <&phy7>;
        phy-mode = "sgmii";
        phys = <&serdes 4 SERDES1G(2)>;
 };
 
 &port5 {
+       status = "okay";
        phy-handle = <&phy4>;
        phy-mode = "sgmii";
        phys = <&serdes 5 SERDES1G(5)>;
 };
 
 &port6 {
+       status = "okay";
        phy-handle = <&phy6>;
        phy-mode = "sgmii";
        phys = <&serdes 6 SERDES1G(3)>;
 };
 
 &port9 {
+       status = "okay";
        phy-handle = <&phy5>;
        phy-mode = "sgmii";
        phys = <&serdes 9 SERDES1G(4)>;

diff --git a/arch/mips/boot/dts/mscc/ocelot_pcb123.dts b/arch/mips/boot/dts/mscc/ocelot_pcb123.dts
index ef852f3..7d7e638 100644 (file)
--- a/arch/mips/boot/dts/mscc/ocelot_pcb123.dts
+++ b/arch/mips/boot/dts/mscc/ocelot_pcb123.dts
@@ -47,17 +47,21 @@
 };
 
 &port0 {
+       status = "okay";
        phy-handle = <&phy0>;
 };
 
 &port1 {
+       status = "okay";
        phy-handle = <&phy1>;
 };
 
 &port2 {
+       status = "okay";
        phy-handle = <&phy2>;
 };
 
 &port3 {
+       status = "okay";
        phy-handle = <&phy3>;
 };