arm64: dts: imx8mm-kontron: Disable pull resistors for SD card signals on BL board

Some signals have external pullup resistors on the board and don't need
the internal ones to be enabled. Due to silicon errata ERR050080 let's
disable the internal pull resistors whererever possible and prevent
any unwanted behavior in case they wear out.

Fixes: 8668d8b2e67f ("arm64: dts: Add the Kontron i.MX8M Mini SoMs and baseboards")
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts b/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts
index ee93db1..aab8e24 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts
@@ -316,40 +316,40 @@
 
        pinctrl_usdhc2: usdhc2grp {
                fsl,pins = <
-                       MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK                 0x190
+                       MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK                 0x90
                        MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD                 0x1d0
                        MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0             0x1d0
                        MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1             0x1d0
                        MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2             0x1d0
                        MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3             0x1d0
-                       MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12                0x019
-                       MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT          0x1d0
+                       MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12                0x19
+                       MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT          0xd0
                >;
        };
 
        pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
                fsl,pins = <
-                       MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK                 0x194
+                       MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK                 0x94
                        MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD                 0x1d4
                        MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0             0x1d4
                        MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1             0x1d4
                        MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2             0x1d4
                        MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3             0x1d4
-                       MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12                0x019
-                       MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT          0x1d0
+                       MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12                0x19
+                       MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT          0xd0
                >;
        };
 
        pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
                fsl,pins = <
-                       MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK                 0x196
+                       MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK                 0x96
                        MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD                 0x1d6
                        MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0             0x1d6
                        MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1             0x1d6
                        MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2             0x1d6
                        MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3             0x1d6
-                       MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12                0x019
-                       MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT          0x1d0
+                       MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12                0x19
+                       MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT          0xd0
                >;
        };
 };