#if defined(CONFIG_ARCH_TEGRA_186_SOC)
static const struct tegra_mc_client tegra186_mc_clients[] = {
{
#if defined(CONFIG_ARCH_TEGRA_186_SOC)
static const struct tegra_mc_client tegra186_mc_clients[] = {
{
+ .id = TEGRA186_MEMORY_CLIENT_PTCR,
.name = "ptcr",
.sid = TEGRA186_SID_PASSTHROUGH,
.regs = {
.name = "ptcr",
.sid = TEGRA186_SID_PASSTHROUGH,
.regs = {
+ .id = TEGRA186_MEMORY_CLIENT_AFIR,
.name = "afir",
.sid = TEGRA186_SID_AFI,
.regs = {
.name = "afir",
.sid = TEGRA186_SID_AFI,
.regs = {
+ .id = TEGRA186_MEMORY_CLIENT_HDAR,
.name = "hdar",
.sid = TEGRA186_SID_HDA,
.regs = {
.name = "hdar",
.sid = TEGRA186_SID_HDA,
.regs = {
+ .id = TEGRA186_MEMORY_CLIENT_HOST1XDMAR,
.name = "host1xdmar",
.sid = TEGRA186_SID_HOST1X,
.regs = {
.name = "host1xdmar",
.sid = TEGRA186_SID_HOST1X,
.regs = {
+ .id = TEGRA186_MEMORY_CLIENT_NVENCSRD,
.name = "nvencsrd",
.sid = TEGRA186_SID_NVENC,
.regs = {
.name = "nvencsrd",
.sid = TEGRA186_SID_NVENC,
.regs = {
+ .id = TEGRA186_MEMORY_CLIENT_SATAR,
.name = "satar",
.sid = TEGRA186_SID_SATA,
.regs = {
.name = "satar",
.sid = TEGRA186_SID_SATA,
.regs = {
+ .id = TEGRA186_MEMORY_CLIENT_MPCORER,
.name = "mpcorer",
.sid = TEGRA186_SID_PASSTHROUGH,
.regs = {
.name = "mpcorer",
.sid = TEGRA186_SID_PASSTHROUGH,
.regs = {
+ .id = TEGRA186_MEMORY_CLIENT_NVENCSWR,
.name = "nvencswr",
.sid = TEGRA186_SID_NVENC,
.regs = {
.name = "nvencswr",
.sid = TEGRA186_SID_NVENC,
.regs = {
+ .id = TEGRA186_MEMORY_CLIENT_AFIW,
.name = "afiw",
.sid = TEGRA186_SID_AFI,
.regs = {
.name = "afiw",
.sid = TEGRA186_SID_AFI,
.regs = {
+ .id = TEGRA186_MEMORY_CLIENT_HDAW,
.name = "hdaw",
.sid = TEGRA186_SID_HDA,
.regs = {
.name = "hdaw",
.sid = TEGRA186_SID_HDA,
.regs = {
+ .id = TEGRA186_MEMORY_CLIENT_MPCOREW,
.name = "mpcorew",
.sid = TEGRA186_SID_PASSTHROUGH,
.regs = {
.name = "mpcorew",
.sid = TEGRA186_SID_PASSTHROUGH,
.regs = {
+ .id = TEGRA186_MEMORY_CLIENT_SATAW,
.name = "sataw",
.sid = TEGRA186_SID_SATA,
.regs = {
.name = "sataw",
.sid = TEGRA186_SID_SATA,
.regs = {
+ .id = TEGRA186_MEMORY_CLIENT_ISPRA,
.name = "ispra",
.sid = TEGRA186_SID_ISP,
.regs = {
.name = "ispra",
.sid = TEGRA186_SID_ISP,
.regs = {
+ .id = TEGRA186_MEMORY_CLIENT_ISPWA,
.name = "ispwa",
.sid = TEGRA186_SID_ISP,
.regs = {
.name = "ispwa",
.sid = TEGRA186_SID_ISP,
.regs = {
+ .id = TEGRA186_MEMORY_CLIENT_ISPWB,
.name = "ispwb",
.sid = TEGRA186_SID_ISP,
.regs = {
.name = "ispwb",
.sid = TEGRA186_SID_ISP,
.regs = {
+ .id = TEGRA186_MEMORY_CLIENT_XUSB_HOSTR,
.name = "xusb_hostr",
.sid = TEGRA186_SID_XUSB_HOST,
.regs = {
.name = "xusb_hostr",
.sid = TEGRA186_SID_XUSB_HOST,
.regs = {
+ .id = TEGRA186_MEMORY_CLIENT_XUSB_HOSTW,
.name = "xusb_hostw",
.sid = TEGRA186_SID_XUSB_HOST,
.regs = {
.name = "xusb_hostw",
.sid = TEGRA186_SID_XUSB_HOST,
.regs = {
+ .id = TEGRA186_MEMORY_CLIENT_XUSB_DEVR,
.name = "xusb_devr",
.sid = TEGRA186_SID_XUSB_DEV,
.regs = {
.name = "xusb_devr",
.sid = TEGRA186_SID_XUSB_DEV,
.regs = {
+ .id = TEGRA186_MEMORY_CLIENT_XUSB_DEVW,
.name = "xusb_devw",
.sid = TEGRA186_SID_XUSB_DEV,
.regs = {
.name = "xusb_devw",
.sid = TEGRA186_SID_XUSB_DEV,
.regs = {
+ .id = TEGRA186_MEMORY_CLIENT_TSECSRD,
.name = "tsecsrd",
.sid = TEGRA186_SID_TSEC,
.regs = {
.name = "tsecsrd",
.sid = TEGRA186_SID_TSEC,
.regs = {
+ .id = TEGRA186_MEMORY_CLIENT_TSECSWR,
.name = "tsecswr",
.sid = TEGRA186_SID_TSEC,
.regs = {
.name = "tsecswr",
.sid = TEGRA186_SID_TSEC,
.regs = {
+ .id = TEGRA186_MEMORY_CLIENT_GPUSRD,
.name = "gpusrd",
.sid = TEGRA186_SID_GPU,
.regs = {
.name = "gpusrd",
.sid = TEGRA186_SID_GPU,
.regs = {
+ .id = TEGRA186_MEMORY_CLIENT_GPUSWR,
.name = "gpuswr",
.sid = TEGRA186_SID_GPU,
.regs = {
.name = "gpuswr",
.sid = TEGRA186_SID_GPU,
.regs = {
+ .id = TEGRA186_MEMORY_CLIENT_SDMMCRA,
.name = "sdmmcra",
.sid = TEGRA186_SID_SDMMC1,
.regs = {
.name = "sdmmcra",
.sid = TEGRA186_SID_SDMMC1,
.regs = {
+ .id = TEGRA186_MEMORY_CLIENT_SDMMCRAA,
.name = "sdmmcraa",
.sid = TEGRA186_SID_SDMMC2,
.regs = {
.name = "sdmmcraa",
.sid = TEGRA186_SID_SDMMC2,
.regs = {
+ .id = TEGRA186_MEMORY_CLIENT_SDMMCR,
.name = "sdmmcr",
.sid = TEGRA186_SID_SDMMC3,
.regs = {
.name = "sdmmcr",
.sid = TEGRA186_SID_SDMMC3,
.regs = {
+ .id = TEGRA186_MEMORY_CLIENT_SDMMCRAB,
.name = "sdmmcrab",
.sid = TEGRA186_SID_SDMMC4,
.regs = {
.name = "sdmmcrab",
.sid = TEGRA186_SID_SDMMC4,
.regs = {
+ .id = TEGRA186_MEMORY_CLIENT_SDMMCWA,
.name = "sdmmcwa",
.sid = TEGRA186_SID_SDMMC1,
.regs = {
.name = "sdmmcwa",
.sid = TEGRA186_SID_SDMMC1,
.regs = {
+ .id = TEGRA186_MEMORY_CLIENT_SDMMCWAA,
.name = "sdmmcwaa",
.sid = TEGRA186_SID_SDMMC2,
.regs = {
.name = "sdmmcwaa",
.sid = TEGRA186_SID_SDMMC2,
.regs = {
+ .id = TEGRA186_MEMORY_CLIENT_SDMMCW,
.name = "sdmmcw",
.sid = TEGRA186_SID_SDMMC3,
.regs = {
.name = "sdmmcw",
.sid = TEGRA186_SID_SDMMC3,
.regs = {
+ .id = TEGRA186_MEMORY_CLIENT_SDMMCWAB,
.name = "sdmmcwab",
.sid = TEGRA186_SID_SDMMC4,
.regs = {
.name = "sdmmcwab",
.sid = TEGRA186_SID_SDMMC4,
.regs = {
+ .id = TEGRA186_MEMORY_CLIENT_VICSRD,
.name = "vicsrd",
.sid = TEGRA186_SID_VIC,
.regs = {
.name = "vicsrd",
.sid = TEGRA186_SID_VIC,
.regs = {
+ .id = TEGRA186_MEMORY_CLIENT_VICSWR,
.name = "vicswr",
.sid = TEGRA186_SID_VIC,
.regs = {
.name = "vicswr",
.sid = TEGRA186_SID_VIC,
.regs = {
+ .id = TEGRA186_MEMORY_CLIENT_VIW,
.name = "viw",
.sid = TEGRA186_SID_VI,
.regs = {
.name = "viw",
.sid = TEGRA186_SID_VI,
.regs = {
+ .id = TEGRA186_MEMORY_CLIENT_NVDECSRD,
.name = "nvdecsrd",
.sid = TEGRA186_SID_NVDEC,
.regs = {
.name = "nvdecsrd",
.sid = TEGRA186_SID_NVDEC,
.regs = {
+ .id = TEGRA186_MEMORY_CLIENT_NVDECSWR,
.name = "nvdecswr",
.sid = TEGRA186_SID_NVDEC,
.regs = {
.name = "nvdecswr",
.sid = TEGRA186_SID_NVDEC,
.regs = {
+ .id = TEGRA186_MEMORY_CLIENT_APER,
.name = "aper",
.sid = TEGRA186_SID_APE,
.regs = {
.name = "aper",
.sid = TEGRA186_SID_APE,
.regs = {
+ .id = TEGRA186_MEMORY_CLIENT_APEW,
.name = "apew",
.sid = TEGRA186_SID_APE,
.regs = {
.name = "apew",
.sid = TEGRA186_SID_APE,
.regs = {
+ .id = TEGRA186_MEMORY_CLIENT_NVJPGSRD,
.name = "nvjpgsrd",
.sid = TEGRA186_SID_NVJPG,
.regs = {
.name = "nvjpgsrd",
.sid = TEGRA186_SID_NVJPG,
.regs = {
+ .id = TEGRA186_MEMORY_CLIENT_NVJPGSWR,
.name = "nvjpgswr",
.sid = TEGRA186_SID_NVJPG,
.regs = {
.name = "nvjpgswr",
.sid = TEGRA186_SID_NVJPG,
.regs = {
+ .id = TEGRA186_MEMORY_CLIENT_SESRD,
.name = "sesrd",
.sid = TEGRA186_SID_SE,
.regs = {
.name = "sesrd",
.sid = TEGRA186_SID_SE,
.regs = {
+ .id = TEGRA186_MEMORY_CLIENT_SESWR,
.name = "seswr",
.sid = TEGRA186_SID_SE,
.regs = {
.name = "seswr",
.sid = TEGRA186_SID_SE,
.regs = {
+ .id = TEGRA186_MEMORY_CLIENT_ETRR,
.name = "etrr",
.sid = TEGRA186_SID_ETR,
.regs = {
.name = "etrr",
.sid = TEGRA186_SID_ETR,
.regs = {
+ .id = TEGRA186_MEMORY_CLIENT_ETRW,
.name = "etrw",
.sid = TEGRA186_SID_ETR,
.regs = {
.name = "etrw",
.sid = TEGRA186_SID_ETR,
.regs = {
+ .id = TEGRA186_MEMORY_CLIENT_TSECSRDB,
.name = "tsecsrdb",
.sid = TEGRA186_SID_TSECB,
.regs = {
.name = "tsecsrdb",
.sid = TEGRA186_SID_TSECB,
.regs = {
+ .id = TEGRA186_MEMORY_CLIENT_TSECSWRB,
.name = "tsecswrb",
.sid = TEGRA186_SID_TSECB,
.regs = {
.name = "tsecswrb",
.sid = TEGRA186_SID_TSECB,
.regs = {
+ .id = TEGRA186_MEMORY_CLIENT_GPUSRD2,
.name = "gpusrd2",
.sid = TEGRA186_SID_GPU,
.regs = {
.name = "gpusrd2",
.sid = TEGRA186_SID_GPU,
.regs = {
+ .id = TEGRA186_MEMORY_CLIENT_GPUSWR2,
.name = "gpuswr2",
.sid = TEGRA186_SID_GPU,
.regs = {
.name = "gpuswr2",
.sid = TEGRA186_SID_GPU,
.regs = {
+ .id = TEGRA186_MEMORY_CLIENT_AXISR,
.name = "axisr",
.sid = TEGRA186_SID_GPCDMA_0,
.regs = {
.name = "axisr",
.sid = TEGRA186_SID_GPCDMA_0,
.regs = {
+ .id = TEGRA186_MEMORY_CLIENT_AXISW,
.name = "axisw",
.sid = TEGRA186_SID_GPCDMA_0,
.regs = {
.name = "axisw",
.sid = TEGRA186_SID_GPCDMA_0,
.regs = {
+ .id = TEGRA186_MEMORY_CLIENT_EQOSR,
.name = "eqosr",
.sid = TEGRA186_SID_EQOS,
.regs = {
.name = "eqosr",
.sid = TEGRA186_SID_EQOS,
.regs = {
+ .id = TEGRA186_MEMORY_CLIENT_EQOSW,
.name = "eqosw",
.sid = TEGRA186_SID_EQOS,
.regs = {
.name = "eqosw",
.sid = TEGRA186_SID_EQOS,
.regs = {
+ .id = TEGRA186_MEMORY_CLIENT_UFSHCR,
.name = "ufshcr",
.sid = TEGRA186_SID_UFSHC,
.regs = {
.name = "ufshcr",
.sid = TEGRA186_SID_UFSHC,
.regs = {
+ .id = TEGRA186_MEMORY_CLIENT_UFSHCW,
.name = "ufshcw",
.sid = TEGRA186_SID_UFSHC,
.regs = {
.name = "ufshcw",
.sid = TEGRA186_SID_UFSHC,
.regs = {
+ .id = TEGRA186_MEMORY_CLIENT_NVDISPLAYR,
.name = "nvdisplayr",
.sid = TEGRA186_SID_NVDISPLAY,
.regs = {
.name = "nvdisplayr",
.sid = TEGRA186_SID_NVDISPLAY,
.regs = {
+ .id = TEGRA186_MEMORY_CLIENT_BPMPR,
.name = "bpmpr",
.sid = TEGRA186_SID_BPMP,
.regs = {
.name = "bpmpr",
.sid = TEGRA186_SID_BPMP,
.regs = {
+ .id = TEGRA186_MEMORY_CLIENT_BPMPW,
.name = "bpmpw",
.sid = TEGRA186_SID_BPMP,
.regs = {
.name = "bpmpw",
.sid = TEGRA186_SID_BPMP,
.regs = {
+ .id = TEGRA186_MEMORY_CLIENT_BPMPDMAR,
.name = "bpmpdmar",
.sid = TEGRA186_SID_BPMP,
.regs = {
.name = "bpmpdmar",
.sid = TEGRA186_SID_BPMP,
.regs = {
+ .id = TEGRA186_MEMORY_CLIENT_BPMPDMAW,
.name = "bpmpdmaw",
.sid = TEGRA186_SID_BPMP,
.regs = {
.name = "bpmpdmaw",
.sid = TEGRA186_SID_BPMP,
.regs = {
+ .id = TEGRA186_MEMORY_CLIENT_AONR,
.name = "aonr",
.sid = TEGRA186_SID_AON,
.regs = {
.name = "aonr",
.sid = TEGRA186_SID_AON,
.regs = {
+ .id = TEGRA186_MEMORY_CLIENT_AONW,
.name = "aonw",
.sid = TEGRA186_SID_AON,
.regs = {
.name = "aonw",
.sid = TEGRA186_SID_AON,
.regs = {
+ .id = TEGRA186_MEMORY_CLIENT_AONDMAR,
.name = "aondmar",
.sid = TEGRA186_SID_AON,
.regs = {
.name = "aondmar",
.sid = TEGRA186_SID_AON,
.regs = {
+ .id = TEGRA186_MEMORY_CLIENT_AONDMAW,
.name = "aondmaw",
.sid = TEGRA186_SID_AON,
.regs = {
.name = "aondmaw",
.sid = TEGRA186_SID_AON,
.regs = {
+ .id = TEGRA186_MEMORY_CLIENT_SCER,
.name = "scer",
.sid = TEGRA186_SID_SCE,
.regs = {
.name = "scer",
.sid = TEGRA186_SID_SCE,
.regs = {
+ .id = TEGRA186_MEMORY_CLIENT_SCEW,
.name = "scew",
.sid = TEGRA186_SID_SCE,
.regs = {
.name = "scew",
.sid = TEGRA186_SID_SCE,
.regs = {
+ .id = TEGRA186_MEMORY_CLIENT_SCEDMAR,
.name = "scedmar",
.sid = TEGRA186_SID_SCE,
.regs = {
.name = "scedmar",
.sid = TEGRA186_SID_SCE,
.regs = {
+ .id = TEGRA186_MEMORY_CLIENT_SCEDMAW,
.name = "scedmaw",
.sid = TEGRA186_SID_SCE,
.regs = {
.name = "scedmaw",
.sid = TEGRA186_SID_SCE,
.regs = {
+ .id = TEGRA186_MEMORY_CLIENT_APEDMAR,
.name = "apedmar",
.sid = TEGRA186_SID_APE,
.regs = {
.name = "apedmar",
.sid = TEGRA186_SID_APE,
.regs = {
+ .id = TEGRA186_MEMORY_CLIENT_APEDMAW,
.name = "apedmaw",
.sid = TEGRA186_SID_APE,
.regs = {
.name = "apedmaw",
.sid = TEGRA186_SID_APE,
.regs = {
+ .id = TEGRA186_MEMORY_CLIENT_NVDISPLAYR1,
.name = "nvdisplayr1",
.sid = TEGRA186_SID_NVDISPLAY,
.regs = {
.name = "nvdisplayr1",
.sid = TEGRA186_SID_NVDISPLAY,
.regs = {
+ .id = TEGRA186_MEMORY_CLIENT_VICSRD1,
.name = "vicsrd1",
.sid = TEGRA186_SID_VIC,
.regs = {
.name = "vicsrd1",
.sid = TEGRA186_SID_VIC,
.regs = {
+ .id = TEGRA186_MEMORY_CLIENT_NVDECSRD1,
.name = "nvdecsrd1",
.sid = TEGRA186_SID_NVDEC,
.regs = {
.name = "nvdecsrd1",
.sid = TEGRA186_SID_NVDEC,
.regs = {
#if defined(CONFIG_ARCH_TEGRA_194_SOC)
static const struct tegra_mc_client tegra194_mc_clients[] = {
{
#if defined(CONFIG_ARCH_TEGRA_194_SOC)
static const struct tegra_mc_client tegra194_mc_clients[] = {
{
+ .id = TEGRA194_MEMORY_CLIENT_PTCR,
.name = "ptcr",
.sid = TEGRA194_SID_PASSTHROUGH,
.regs = {
.name = "ptcr",
.sid = TEGRA194_SID_PASSTHROUGH,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_MIU7R,
.name = "miu7r",
.sid = TEGRA194_SID_MIU,
.regs = {
.name = "miu7r",
.sid = TEGRA194_SID_MIU,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_MIU7W,
.name = "miu7w",
.sid = TEGRA194_SID_MIU,
.regs = {
.name = "miu7w",
.sid = TEGRA194_SID_MIU,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_HDAR,
.name = "hdar",
.sid = TEGRA194_SID_HDA,
.regs = {
.name = "hdar",
.sid = TEGRA194_SID_HDA,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_HOST1XDMAR,
.name = "host1xdmar",
.sid = TEGRA194_SID_HOST1X,
.regs = {
.name = "host1xdmar",
.sid = TEGRA194_SID_HOST1X,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_NVENCSRD,
.name = "nvencsrd",
.sid = TEGRA194_SID_NVENC,
.regs = {
.name = "nvencsrd",
.sid = TEGRA194_SID_NVENC,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_SATAR,
.name = "satar",
.sid = TEGRA194_SID_SATA,
.regs = {
.name = "satar",
.sid = TEGRA194_SID_SATA,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_MPCORER,
.name = "mpcorer",
.sid = TEGRA194_SID_PASSTHROUGH,
.regs = {
.name = "mpcorer",
.sid = TEGRA194_SID_PASSTHROUGH,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_NVENCSWR,
.name = "nvencswr",
.sid = TEGRA194_SID_NVENC,
.regs = {
.name = "nvencswr",
.sid = TEGRA194_SID_NVENC,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_HDAW,
.name = "hdaw",
.sid = TEGRA194_SID_HDA,
.regs = {
.name = "hdaw",
.sid = TEGRA194_SID_HDA,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_MPCOREW,
.name = "mpcorew",
.sid = TEGRA194_SID_PASSTHROUGH,
.regs = {
.name = "mpcorew",
.sid = TEGRA194_SID_PASSTHROUGH,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_SATAW,
.name = "sataw",
.sid = TEGRA194_SID_SATA,
.regs = {
.name = "sataw",
.sid = TEGRA194_SID_SATA,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_ISPRA,
.name = "ispra",
.sid = TEGRA194_SID_ISP,
.regs = {
.name = "ispra",
.sid = TEGRA194_SID_ISP,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_ISPFALR,
.name = "ispfalr",
.sid = TEGRA194_SID_ISP_FALCON,
.regs = {
.name = "ispfalr",
.sid = TEGRA194_SID_ISP_FALCON,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_ISPWA,
.name = "ispwa",
.sid = TEGRA194_SID_ISP,
.regs = {
.name = "ispwa",
.sid = TEGRA194_SID_ISP,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_ISPWB,
.name = "ispwb",
.sid = TEGRA194_SID_ISP,
.regs = {
.name = "ispwb",
.sid = TEGRA194_SID_ISP,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_XUSB_HOSTR,
.name = "xusb_hostr",
.sid = TEGRA194_SID_XUSB_HOST,
.regs = {
.name = "xusb_hostr",
.sid = TEGRA194_SID_XUSB_HOST,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_XUSB_HOSTW,
.name = "xusb_hostw",
.sid = TEGRA194_SID_XUSB_HOST,
.regs = {
.name = "xusb_hostw",
.sid = TEGRA194_SID_XUSB_HOST,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_XUSB_DEVR,
.name = "xusb_devr",
.sid = TEGRA194_SID_XUSB_DEV,
.regs = {
.name = "xusb_devr",
.sid = TEGRA194_SID_XUSB_DEV,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_XUSB_DEVW,
.name = "xusb_devw",
.sid = TEGRA194_SID_XUSB_DEV,
.regs = {
.name = "xusb_devw",
.sid = TEGRA194_SID_XUSB_DEV,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_SDMMCRA,
.name = "sdmmcra",
.sid = TEGRA194_SID_SDMMC1,
.regs = {
.name = "sdmmcra",
.sid = TEGRA194_SID_SDMMC1,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_SDMMCR,
.name = "sdmmcr",
.sid = TEGRA194_SID_SDMMC3,
.regs = {
.name = "sdmmcr",
.sid = TEGRA194_SID_SDMMC3,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_SDMMCRAB,
.name = "sdmmcrab",
.sid = TEGRA194_SID_SDMMC4,
.regs = {
.name = "sdmmcrab",
.sid = TEGRA194_SID_SDMMC4,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_SDMMCWA,
.name = "sdmmcwa",
.sid = TEGRA194_SID_SDMMC1,
.regs = {
.name = "sdmmcwa",
.sid = TEGRA194_SID_SDMMC1,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_SDMMCW,
.name = "sdmmcw",
.sid = TEGRA194_SID_SDMMC3,
.regs = {
.name = "sdmmcw",
.sid = TEGRA194_SID_SDMMC3,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_SDMMCWAB,
.name = "sdmmcwab",
.sid = TEGRA194_SID_SDMMC4,
.regs = {
.name = "sdmmcwab",
.sid = TEGRA194_SID_SDMMC4,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_VICSRD,
.name = "vicsrd",
.sid = TEGRA194_SID_VIC,
.regs = {
.name = "vicsrd",
.sid = TEGRA194_SID_VIC,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_VICSWR,
.name = "vicswr",
.sid = TEGRA194_SID_VIC,
.regs = {
.name = "vicswr",
.sid = TEGRA194_SID_VIC,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_VIW,
.name = "viw",
.sid = TEGRA194_SID_VI,
.regs = {
.name = "viw",
.sid = TEGRA194_SID_VI,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_NVDECSRD,
.name = "nvdecsrd",
.sid = TEGRA194_SID_NVDEC,
.regs = {
.name = "nvdecsrd",
.sid = TEGRA194_SID_NVDEC,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_NVDECSWR,
.name = "nvdecswr",
.sid = TEGRA194_SID_NVDEC,
.regs = {
.name = "nvdecswr",
.sid = TEGRA194_SID_NVDEC,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_APER,
.name = "aper",
.sid = TEGRA194_SID_APE,
.regs = {
.name = "aper",
.sid = TEGRA194_SID_APE,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_APEW,
.name = "apew",
.sid = TEGRA194_SID_APE,
.regs = {
.name = "apew",
.sid = TEGRA194_SID_APE,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_NVJPGSRD,
.name = "nvjpgsrd",
.sid = TEGRA194_SID_NVJPG,
.regs = {
.name = "nvjpgsrd",
.sid = TEGRA194_SID_NVJPG,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_NVJPGSWR,
.name = "nvjpgswr",
.sid = TEGRA194_SID_NVJPG,
.regs = {
.name = "nvjpgswr",
.sid = TEGRA194_SID_NVJPG,
.regs = {
},
}, {
.name = "axiapr",
},
}, {
.name = "axiapr",
+ .id = TEGRA194_MEMORY_CLIENT_AXIAPR,
.sid = TEGRA194_SID_PASSTHROUGH,
.regs = {
.sid = {
.sid = TEGRA194_SID_PASSTHROUGH,
.regs = {
.sid = {
+ .id = TEGRA194_MEMORY_CLIENT_AXIAPW,
.name = "axiapw",
.sid = TEGRA194_SID_PASSTHROUGH,
.regs = {
.name = "axiapw",
.sid = TEGRA194_SID_PASSTHROUGH,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_ETRR,
.name = "etrr",
.sid = TEGRA194_SID_ETR,
.regs = {
.name = "etrr",
.sid = TEGRA194_SID_ETR,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_ETRW,
.name = "etrw",
.sid = TEGRA194_SID_ETR,
.regs = {
.name = "etrw",
.sid = TEGRA194_SID_ETR,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_AXISR,
.name = "axisr",
.sid = TEGRA194_SID_PASSTHROUGH,
.regs = {
.name = "axisr",
.sid = TEGRA194_SID_PASSTHROUGH,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_AXISW,
.name = "axisw",
.sid = TEGRA194_SID_PASSTHROUGH,
.regs = {
.name = "axisw",
.sid = TEGRA194_SID_PASSTHROUGH,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_EQOSR,
.name = "eqosr",
.sid = TEGRA194_SID_EQOS,
.regs = {
.name = "eqosr",
.sid = TEGRA194_SID_EQOS,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_EQOSW,
.sid = TEGRA194_SID_EQOS,
.regs = {
.sid = {
.sid = TEGRA194_SID_EQOS,
.regs = {
.sid = {
+ .id = TEGRA194_MEMORY_CLIENT_UFSHCR,
.name = "ufshcr",
.sid = TEGRA194_SID_UFSHC,
.regs = {
.name = "ufshcr",
.sid = TEGRA194_SID_UFSHC,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_UFSHCW,
.name = "ufshcw",
.sid = TEGRA194_SID_UFSHC,
.regs = {
.name = "ufshcw",
.sid = TEGRA194_SID_UFSHC,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_NVDISPLAYR,
.name = "nvdisplayr",
.sid = TEGRA194_SID_NVDISPLAY,
.regs = {
.name = "nvdisplayr",
.sid = TEGRA194_SID_NVDISPLAY,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_BPMPR,
.name = "bpmpr",
.sid = TEGRA194_SID_BPMP,
.regs = {
.name = "bpmpr",
.sid = TEGRA194_SID_BPMP,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_BPMPW,
.name = "bpmpw",
.sid = TEGRA194_SID_BPMP,
.regs = {
.name = "bpmpw",
.sid = TEGRA194_SID_BPMP,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_BPMPDMAR,
.name = "bpmpdmar",
.sid = TEGRA194_SID_BPMP,
.regs = {
.name = "bpmpdmar",
.sid = TEGRA194_SID_BPMP,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_BPMPDMAW,
.name = "bpmpdmaw",
.sid = TEGRA194_SID_BPMP,
.regs = {
.name = "bpmpdmaw",
.sid = TEGRA194_SID_BPMP,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_AONR,
.name = "aonr",
.sid = TEGRA194_SID_AON,
.regs = {
.name = "aonr",
.sid = TEGRA194_SID_AON,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_AONW,
.name = "aonw",
.sid = TEGRA194_SID_AON,
.regs = {
.name = "aonw",
.sid = TEGRA194_SID_AON,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_AONDMAR,
.name = "aondmar",
.sid = TEGRA194_SID_AON,
.regs = {
.name = "aondmar",
.sid = TEGRA194_SID_AON,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_AONDMAW,
.name = "aondmaw",
.sid = TEGRA194_SID_AON,
.regs = {
.name = "aondmaw",
.sid = TEGRA194_SID_AON,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_SCER,
.name = "scer",
.sid = TEGRA194_SID_SCE,
.regs = {
.name = "scer",
.sid = TEGRA194_SID_SCE,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_SCEW,
.name = "scew",
.sid = TEGRA194_SID_SCE,
.regs = {
.name = "scew",
.sid = TEGRA194_SID_SCE,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_SCEDMAR,
.name = "scedmar",
.sid = TEGRA194_SID_SCE,
.regs = {
.name = "scedmar",
.sid = TEGRA194_SID_SCE,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_SCEDMAW,
.name = "scedmaw",
.sid = TEGRA194_SID_SCE,
.regs = {
.name = "scedmaw",
.sid = TEGRA194_SID_SCE,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_APEDMAR,
.name = "apedmar",
.sid = TEGRA194_SID_APE,
.regs = {
.name = "apedmar",
.sid = TEGRA194_SID_APE,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_APEDMAW,
.name = "apedmaw",
.sid = TEGRA194_SID_APE,
.regs = {
.name = "apedmaw",
.sid = TEGRA194_SID_APE,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_NVDISPLAYR1,
.name = "nvdisplayr1",
.sid = TEGRA194_SID_NVDISPLAY,
.regs = {
.name = "nvdisplayr1",
.sid = TEGRA194_SID_NVDISPLAY,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_VICSRD1,
.name = "vicsrd1",
.sid = TEGRA194_SID_VIC,
.regs = {
.name = "vicsrd1",
.sid = TEGRA194_SID_VIC,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_NVDECSRD1,
.name = "nvdecsrd1",
.sid = TEGRA194_SID_NVDEC,
.regs = {
.name = "nvdecsrd1",
.sid = TEGRA194_SID_NVDEC,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_MIU0R,
.name = "miu0r",
.sid = TEGRA194_SID_MIU,
.regs = {
.name = "miu0r",
.sid = TEGRA194_SID_MIU,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_MIU0W,
.sid = TEGRA194_SID_MIU,
.regs = {
.sid = {
.sid = TEGRA194_SID_MIU,
.regs = {
.sid = {
+ .id = TEGRA194_MEMORY_CLIENT_MIU1R,
.name = "miu1r",
.sid = TEGRA194_SID_MIU,
.regs = {
.name = "miu1r",
.sid = TEGRA194_SID_MIU,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_MIU1W,
.name = "miu1w",
.sid = TEGRA194_SID_MIU,
.regs = {
.name = "miu1w",
.sid = TEGRA194_SID_MIU,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_MIU2R,
.name = "miu2r",
.sid = TEGRA194_SID_MIU,
.regs = {
.name = "miu2r",
.sid = TEGRA194_SID_MIU,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_MIU2W,
.name = "miu2w",
.sid = TEGRA194_SID_MIU,
.regs = {
.name = "miu2w",
.sid = TEGRA194_SID_MIU,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_MIU3R,
.name = "miu3r",
.sid = TEGRA194_SID_MIU,
.regs = {
.name = "miu3r",
.sid = TEGRA194_SID_MIU,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_MIU3W,
.name = "miu3w",
.sid = TEGRA194_SID_MIU,
.regs = {
.name = "miu3w",
.sid = TEGRA194_SID_MIU,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_MIU4R,
.name = "miu4r",
.sid = TEGRA194_SID_MIU,
.regs = {
.name = "miu4r",
.sid = TEGRA194_SID_MIU,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_MIU4W,
.name = "miu4w",
.sid = TEGRA194_SID_MIU,
.regs = {
.name = "miu4w",
.sid = TEGRA194_SID_MIU,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_DPMUR,
.name = "dpmur",
.sid = TEGRA194_SID_PASSTHROUGH,
.regs = {
.name = "dpmur",
.sid = TEGRA194_SID_PASSTHROUGH,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_VIFALR,
.name = "vifalr",
.sid = TEGRA194_SID_VI_FALCON,
.regs = {
.name = "vifalr",
.sid = TEGRA194_SID_VI_FALCON,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_VIFALW,
.name = "vifalw",
.sid = TEGRA194_SID_VI_FALCON,
.regs = {
.name = "vifalw",
.sid = TEGRA194_SID_VI_FALCON,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_DLA0RDA,
.name = "dla0rda",
.sid = TEGRA194_SID_NVDLA0,
.regs = {
.name = "dla0rda",
.sid = TEGRA194_SID_NVDLA0,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_DLA0FALRDB,
.name = "dla0falrdb",
.sid = TEGRA194_SID_NVDLA0,
.regs = {
.name = "dla0falrdb",
.sid = TEGRA194_SID_NVDLA0,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_DLA0WRA,
.name = "dla0wra",
.sid = TEGRA194_SID_NVDLA0,
.regs = {
.name = "dla0wra",
.sid = TEGRA194_SID_NVDLA0,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_DLA0FALWRB,
.name = "dla0falwrb",
.sid = TEGRA194_SID_NVDLA0,
.regs = {
.name = "dla0falwrb",
.sid = TEGRA194_SID_NVDLA0,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_DLA1RDA,
.name = "dla1rda",
.sid = TEGRA194_SID_NVDLA1,
.regs = {
.name = "dla1rda",
.sid = TEGRA194_SID_NVDLA1,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_DLA1FALRDB,
.name = "dla1falrdb",
.sid = TEGRA194_SID_NVDLA1,
.regs = {
.name = "dla1falrdb",
.sid = TEGRA194_SID_NVDLA1,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_DLA1WRA,
.name = "dla1wra",
.sid = TEGRA194_SID_NVDLA1,
.regs = {
.name = "dla1wra",
.sid = TEGRA194_SID_NVDLA1,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_DLA1FALWRB,
.name = "dla1falwrb",
.sid = TEGRA194_SID_NVDLA1,
.regs = {
.name = "dla1falwrb",
.sid = TEGRA194_SID_NVDLA1,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_PVA0RDA,
.name = "pva0rda",
.sid = TEGRA194_SID_PVA0,
.regs = {
.name = "pva0rda",
.sid = TEGRA194_SID_PVA0,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_PVA0RDB,
.name = "pva0rdb",
.sid = TEGRA194_SID_PVA0,
.regs = {
.name = "pva0rdb",
.sid = TEGRA194_SID_PVA0,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_PVA0RDC,
.name = "pva0rdc",
.sid = TEGRA194_SID_PVA0,
.regs = {
.name = "pva0rdc",
.sid = TEGRA194_SID_PVA0,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_PVA0WRA,
.name = "pva0wra",
.sid = TEGRA194_SID_PVA0,
.regs = {
.name = "pva0wra",
.sid = TEGRA194_SID_PVA0,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_PVA0WRB,
.name = "pva0wrb",
.sid = TEGRA194_SID_PVA0,
.regs = {
.name = "pva0wrb",
.sid = TEGRA194_SID_PVA0,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_PVA0WRC,
.name = "pva0wrc",
.sid = TEGRA194_SID_PVA0,
.regs = {
.name = "pva0wrc",
.sid = TEGRA194_SID_PVA0,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_PVA1RDA,
.name = "pva1rda",
.sid = TEGRA194_SID_PVA1,
.regs = {
.name = "pva1rda",
.sid = TEGRA194_SID_PVA1,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_PVA1RDB,
.name = "pva1rdb",
.sid = TEGRA194_SID_PVA1,
.regs = {
.name = "pva1rdb",
.sid = TEGRA194_SID_PVA1,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_PVA1RDC,
.name = "pva1rdc",
.sid = TEGRA194_SID_PVA1,
.regs = {
.name = "pva1rdc",
.sid = TEGRA194_SID_PVA1,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_PVA1WRA,
.name = "pva1wra",
.sid = TEGRA194_SID_PVA1,
.regs = {
.name = "pva1wra",
.sid = TEGRA194_SID_PVA1,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_PVA1WRB,
.name = "pva1wrb",
.sid = TEGRA194_SID_PVA1,
.regs = {
.name = "pva1wrb",
.sid = TEGRA194_SID_PVA1,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_PVA1WRC,
.name = "pva1wrc",
.sid = TEGRA194_SID_PVA1,
.regs = {
.name = "pva1wrc",
.sid = TEGRA194_SID_PVA1,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_RCER,
.name = "rcer",
.sid = TEGRA194_SID_RCE,
.regs = {
.name = "rcer",
.sid = TEGRA194_SID_RCE,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_RCEW,
.name = "rcew",
.sid = TEGRA194_SID_RCE,
.regs = {
.name = "rcew",
.sid = TEGRA194_SID_RCE,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_RCEDMAR,
.name = "rcedmar",
.sid = TEGRA194_SID_RCE,
.regs = {
.name = "rcedmar",
.sid = TEGRA194_SID_RCE,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_RCEDMAW,
.name = "rcedmaw",
.sid = TEGRA194_SID_RCE,
.regs = {
.name = "rcedmaw",
.sid = TEGRA194_SID_RCE,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_NVENC1SRD,
.name = "nvenc1srd",
.sid = TEGRA194_SID_NVENC1,
.regs = {
.name = "nvenc1srd",
.sid = TEGRA194_SID_NVENC1,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_NVENC1SWR,
.name = "nvenc1swr",
.sid = TEGRA194_SID_NVENC1,
.regs = {
.name = "nvenc1swr",
.sid = TEGRA194_SID_NVENC1,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_PCIE0R,
.name = "pcie0r",
.sid = TEGRA194_SID_PCIE0,
.regs = {
.name = "pcie0r",
.sid = TEGRA194_SID_PCIE0,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_PCIE0W,
.name = "pcie0w",
.sid = TEGRA194_SID_PCIE0,
.regs = {
.name = "pcie0w",
.sid = TEGRA194_SID_PCIE0,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_PCIE1R,
.name = "pcie1r",
.sid = TEGRA194_SID_PCIE1,
.regs = {
.name = "pcie1r",
.sid = TEGRA194_SID_PCIE1,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_PCIE1W,
.name = "pcie1w",
.sid = TEGRA194_SID_PCIE1,
.regs = {
.name = "pcie1w",
.sid = TEGRA194_SID_PCIE1,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_PCIE2AR,
.name = "pcie2ar",
.sid = TEGRA194_SID_PCIE2,
.regs = {
.name = "pcie2ar",
.sid = TEGRA194_SID_PCIE2,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_PCIE2AW,
.name = "pcie2aw",
.sid = TEGRA194_SID_PCIE2,
.regs = {
.name = "pcie2aw",
.sid = TEGRA194_SID_PCIE2,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_PCIE3R,
.name = "pcie3r",
.sid = TEGRA194_SID_PCIE3,
.regs = {
.name = "pcie3r",
.sid = TEGRA194_SID_PCIE3,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_PCIE3W,
.name = "pcie3w",
.sid = TEGRA194_SID_PCIE3,
.regs = {
.name = "pcie3w",
.sid = TEGRA194_SID_PCIE3,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_PCIE4R,
.name = "pcie4r",
.sid = TEGRA194_SID_PCIE4,
.regs = {
.name = "pcie4r",
.sid = TEGRA194_SID_PCIE4,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_PCIE4W,
.name = "pcie4w",
.sid = TEGRA194_SID_PCIE4,
.regs = {
.name = "pcie4w",
.sid = TEGRA194_SID_PCIE4,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_PCIE5R,
.name = "pcie5r",
.sid = TEGRA194_SID_PCIE5,
.regs = {
.name = "pcie5r",
.sid = TEGRA194_SID_PCIE5,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_PCIE5W,
.name = "pcie5w",
.sid = TEGRA194_SID_PCIE5,
.regs = {
.name = "pcie5w",
.sid = TEGRA194_SID_PCIE5,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_ISPFALW,
.name = "ispfalw",
.sid = TEGRA194_SID_ISP_FALCON,
.regs = {
.name = "ispfalw",
.sid = TEGRA194_SID_ISP_FALCON,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_DLA0RDA1,
.name = "dla0rda1",
.sid = TEGRA194_SID_NVDLA0,
.regs = {
.name = "dla0rda1",
.sid = TEGRA194_SID_NVDLA0,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_DLA1RDA1,
.name = "dla1rda1",
.sid = TEGRA194_SID_NVDLA1,
.regs = {
.name = "dla1rda1",
.sid = TEGRA194_SID_NVDLA1,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_PVA0RDA1,
.name = "pva0rda1",
.sid = TEGRA194_SID_PVA0,
.regs = {
.name = "pva0rda1",
.sid = TEGRA194_SID_PVA0,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_PVA0RDB1,
.name = "pva0rdb1",
.sid = TEGRA194_SID_PVA0,
.regs = {
.name = "pva0rdb1",
.sid = TEGRA194_SID_PVA0,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_PVA1RDA1,
.name = "pva1rda1",
.sid = TEGRA194_SID_PVA1,
.regs = {
.name = "pva1rda1",
.sid = TEGRA194_SID_PVA1,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_PVA1RDB1,
.name = "pva1rdb1",
.sid = TEGRA194_SID_PVA1,
.regs = {
.name = "pva1rdb1",
.sid = TEGRA194_SID_PVA1,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_PCIE5R1,
.name = "pcie5r1",
.sid = TEGRA194_SID_PCIE5,
.regs = {
.name = "pcie5r1",
.sid = TEGRA194_SID_PCIE5,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_NVENCSRD1,
.name = "nvencsrd1",
.sid = TEGRA194_SID_NVENC,
.regs = {
.name = "nvencsrd1",
.sid = TEGRA194_SID_NVENC,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_NVENC1SRD1,
.name = "nvenc1srd1",
.sid = TEGRA194_SID_NVENC1,
.regs = {
.name = "nvenc1srd1",
.sid = TEGRA194_SID_NVENC1,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_ISPRA1,
.name = "ispra1",
.sid = TEGRA194_SID_ISP,
.regs = {
.name = "ispra1",
.sid = TEGRA194_SID_ISP,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_PCIE0R1,
.name = "pcie0r1",
.sid = TEGRA194_SID_PCIE0,
.regs = {
.name = "pcie0r1",
.sid = TEGRA194_SID_PCIE0,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_NVDEC1SRD,
.name = "nvdec1srd",
.sid = TEGRA194_SID_NVDEC1,
.regs = {
.name = "nvdec1srd",
.sid = TEGRA194_SID_NVDEC1,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_NVDEC1SRD1,
.name = "nvdec1srd1",
.sid = TEGRA194_SID_NVDEC1,
.regs = {
.name = "nvdec1srd1",
.sid = TEGRA194_SID_NVDEC1,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_NVDEC1SWR,
.name = "nvdec1swr",
.sid = TEGRA194_SID_NVDEC1,
.regs = {
.name = "nvdec1swr",
.sid = TEGRA194_SID_NVDEC1,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_MIU5R,
.name = "miu5r",
.sid = TEGRA194_SID_MIU,
.regs = {
.name = "miu5r",
.sid = TEGRA194_SID_MIU,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_MIU5W,
.name = "miu5w",
.sid = TEGRA194_SID_MIU,
.regs = {
.name = "miu5w",
.sid = TEGRA194_SID_MIU,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_MIU6R,
.name = "miu6r",
.sid = TEGRA194_SID_MIU,
.regs = {
.name = "miu6r",
.sid = TEGRA194_SID_MIU,
.regs = {
+ .id = TEGRA194_MEMORY_CLIENT_MIU6W,
.name = "miu6w",
.sid = TEGRA194_SID_MIU,
.regs = {
.name = "miu6w",
.sid = TEGRA194_SID_MIU,
.regs = {