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dt-bindings: soc: Add new board description for MicroBlaze V
authorMichal Simek <michal.simek@amd.com>
Thu, 23 Nov 2023 07:02:28 +0000 (08:02 +0100)
committerMichal Simek <michal.simek@amd.com>
Wed, 13 Dec 2023 15:52:47 +0000 (16:52 +0100)
commitfc622c97d3e290437bb48d2fcb0987dd73234b90
tree82b6a844ce244dfa56cb584d8ea273d3310137cetree | snapshot
parent6f3ecaea6324e77ad9d8f4a27345f59f47b5025fcommit | diff
dt-bindings: soc: Add new board description for MicroBlaze V

MicroBlaze V is new AMD/Xilinx soft-core 32bit RISC-V processor IP.
It is hardware compatible with classic MicroBlaze processor. Processor can
be used with standard AMD/Xilinx IPs including interrupt controller and
timer.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml diff | blob | history
MicroBlaze GIT Repository