ARM: net: bpf: fix zero right shift
authorRabin Vincent <rabin@rab.in>
Tue, 5 Jan 2016 17:34:04 +0000 (18:34 +0100)
committerDavid S. Miller <davem@davemloft.net>
Wed, 6 Jan 2016 06:32:09 +0000 (01:32 -0500)
commitf941461c925832fbeb7876b794ab9fbec6a7a8af
tree96cca8032172841f4514e2f5e721c09b38f368b4
parent60aa3b080a3d2b408af2ca114edb3efc84ad1838
ARM: net: bpf: fix zero right shift

The LSR instruction cannot be used to perform a zero right shift since a
0 as the immediate value (imm5) in the LSR instruction encoding means
that a shift of 32 is perfomed.  See DecodeIMMShift() in the ARM ARM.

Make the JIT skip generation of the LSR if a zero-shift is requested.

This was found using american fuzzy lop.

Signed-off-by: Rabin Vincent <rabin@rab.in>
Acked-by: Alexei Starovoitov <ast@kernel.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
arch/arm/net/bpf_jit_32.c