drm/amd/display: Fix DTBCLK disable requests and SRC_SEL programming
authorAlvin Lee <Alvin.Lee2@amd.com>
Sat, 19 Nov 2022 16:42:41 +0000 (11:42 -0500)
committerAlex Deucher <alexander.deucher@amd.com>
Tue, 29 Nov 2022 16:03:38 +0000 (11:03 -0500)
commitf6015da7f2410109bd2ccd2e2828f26185aeb81d
tree6336377699b432b0ba4cb7898a7794064102ab3f
parent7a259c6df9010fb9508dcbf34a3f5f16993ca37b
drm/amd/display: Fix DTBCLK disable requests and SRC_SEL programming

[Description]
- When transitioning FRL / DP2 is not required, we will always request
  DTBCLK = 0Mhz, but PMFW returns the min freq
- This causes us to make DTBCLK requests every time we call optimize
  after transitioning from FRL to non-FRL
- If DTBCLK is not required, request the min instead (then we only need
  to make 1 extra request at boot time)
- Also when programming PIPE_DTO_SRC_SEL, don't programming for DP
  first, just programming once for the required selection (programming
  DP on an HDMI connection then switching back causes corruption)

Reviewed-by: Dillon Varone <Dillon.Varone@amd.com>
Acked-by: Jasdeep Dhillon <jdhillon@amd.com>
Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c